An Arbitrary Digital Power Noise Generator Using 65nm CMOS Technology
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概要
- 論文の詳細を見る
An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2mm2 in a 65nm 1.2V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.
- （社）電子情報通信学会の論文
- 2010-06-01
著者
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NAGATA Makoto
Graduate School of System Informatics, Kobe University
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HAMANISHI Naoyuki
Toshiba Corporation, Semiconductor Company
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Matsuno Tetsuro
Graduate School Of System Informatics Kobe University
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Kosaka Daisuke
A-r-tec Corporation
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FUJIMOTO Daisuke
Graduate School of System Informatics, Kobe University
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TANABE Ken
Toshiba Corporation
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SHIOCHI Masazumi
Toshiba Corporation
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Nagata Makoto
Graduate School Of System Informatics Kobe University
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Fujimoto Daisuke
Graduate School Of System Informatics Kobe University
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Hamanishi Naoyuki
Toshiba Corporation
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Nagata Makoto
Department Of Computer And Systems Engineering Kobe University:a-r-tec Corporation
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