Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout
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概要
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This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-centered 6T SRAM cells.
著者
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Nii Koji
Renesas Electronics Corporation
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Kawaguchi Hiroshi
Kobe Univ. Kobe‐shi Jpn
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OKUMURA Shunsuke
Kobe University
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YOSHIMOTO Shusuke
Kobe University
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YOSHIMOTO Masahiko
JST CREST
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