Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration
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概要
- 論文の詳細を見る
An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random Vth variation is derived. A three-step approach using characteristic points of the half cell inverters transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low VDD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90nm CMOS LSTP device. Closely correlated dependency on parameters such as Vth, the W ratio, and VDD were obtained. Maximum error measured in the VDD range of 0.6-1.6V was 16mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.
- （社）電子情報通信学会の論文
- 2008-09-01
著者
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Nii Koji
Renesas Electronics Corporation
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Nii Koji
Renesas Technology Corporation
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Onodera Hidetoshi
Graduate School Of Informatics Kyoto University
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SHINOHARA Hirofumi
Renesas Technology Corporation
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ONODERA Hidetoshi
Graduate School of Informatics, Kyoto University
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