Onodera Hidetoshi | Graduate School Of Informatics Kyoto University

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著作論文

Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era(Digital, Low-Power LSI and Low-Power IP)
A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era(Electronic Circuits)
C-12-60 Accurate Individual Gate Delay Measurement to Study Within-die Variations
Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration
Architecture and Performance Evaluation of a New Functional Memory : Functional Memory for Addition (Special Section on VLSI Design and CAD Algorithms)
A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization (Special Section on VLSI for Digital Signal Processing)
An Efficient Motion Estimation Algorithm Using a Gyro Sensor(Video/Image Coding)(Applications and Implementations of Digital Signal Processing)
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures

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