Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers(<Special Section>Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
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概要
- 論文の詳細を見る
This paper proposes an instruction-level power estimation method for an embedded RISC processor, the power consumption of which fluctuates so much by applications and input data. The proposed method estimates the power consumption from the result of ISS (Instruction Set Simulator) and energy tables according to Hamming Distance of Registers (HDR) of all instructions. It is over 10^5 times faster than the gate-level detailed logic simulation, while the estimated power curves have the same tendency with those from the logic simulation. The proposed method realizes both accurate and fast power estimation of embedded processors.
- 2004-04-01
著者
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小野寺 秀俊
京都大学工学部電子工学科
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Onodera Hidetoshi
Department of Communications and Computer Engineering, Kyoto University
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Kobayashi K
Toyama Prefectural Univ. Toyama‐ken Jpn
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Onodera H
Kyoto Univ. Kyoto‐shi Jpn
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Onodera Hidetoshi
Kyoto Univ. Kyoto‐shi Jpn
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Onodera Hidetoshi
Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit
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小野寺 秀俊
滋賀県立大学工学部
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Kobayashi Kazutoshi
Graduate School Of Informatics Kyoto University
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Onodera Hidetoshi
Graduate School Of Informatics Kyoto University
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HIGUCHI Akihiko
Department of Communications and Computer Engineering, Kyoto University
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KOBAYASHI Kazutoshi
VLSI Design and Education Center, The University of Tokyo
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小野寺 秀俊
京都大学大学院工学研究科電子通信工学専攻
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Kobayashi Kazutoshi
Vlsi Design And Education Center The University Of Tokyo
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Kobayashi K
Yamatake Corporation
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Kobayashi K
Graduate School Of Informatics Kyoto University
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Higuchi Akihiko
Graduate School Of Informatics Kyoto University:(present Office)matsushita Electric Co. Ltd.
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Onodera Hidetoshi
Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan
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