Crosstalk Noise Optimization by Post-Layout Transistor Sizing(Physical Design)(<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper proposes a post-layout transistor sizing method for crosstalk noise reduction. The proposed method downsizes the drivers of aggressor wires for noise reduction, utilizing the precise interconnect information extracted from the detail-routed layouts. We develop a transistor sizing algorithm for crosstalk noise reduction under delay constraints, and construct a crosstalk noise optimization method utilizing an analytic crosstalk noise model and a transistor sizing framework that have been developed. Our method exploits the transistor sizing framework that can vary transistor widths inside cells with interconnects unchanged. Our optimization method therefore never causes a new crosstalk noise problem, and does not need iterative layout optimization. The effectiveness of the proposed method is experimentally examined using 2 circuits. The maximum noise voltage is reduced by more than 50% without delay violation. These results show that the risk of crosstalk noise problems can be considerably reduced after detail-routing.

• 社団法人電子情報通信学会の論文
• 2004-12-01

著者

• Onodera Hidetoshi

  Department of Communications and Computer Engineering, Kyoto University

• Onodera Hidetoshi

  Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit

• HASHIMOTO Masanori

  Department of Information Systems Engineering, Osaka University

• Onodera Hidetoshi

  Department Of Information Systems Engineering Osaka University

• Hashimoto Masanori

  Department Of Communications And Computer Engineering Kyoto University

• Hashimoto Masanori

  Department Of Breast And Endocrine Surgery University Of Tokyo

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