A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits

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概要

• 論文の詳細を見る

• We present a method for power and delay optimization by input reordering. We observe that the reordering has a significant effect on the power dissipation of the gate which drives the reordered gate. This is because the input capacitance depends on the signal values of other inputs. This property, however, has not been utilized for power reduction. Previous approaches focus on the reduction of the power dissipated by internal capacitances of the reordered gate. We propose a heuristic algorithm considering the total power consumed in the driving gate and the reordered gate. Experimental results using 30 benchmark circuits show that our method reduces the power dissipation in all the circuits by 5.9% on average. There is a possibility that power dissipation is reduced by 22.5% maximum. In the case of delay and power optimization, our method reduces delay by 6.7% and power dissipation by 5.3% on average.

• 社団法人電子情報通信学会の論文
• 1999-01-25

著者

• Onodera Hidetoshi

  Department of Communications and Computer Engineering, Kyoto University

• Onodera Hidetoshi

  Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit

• HASHIMOTO Masanori

  Department of Information Systems Engineering, Osaka University

• TAMARU Keikichi

  Department of Electronics and Communication, Graduate School of Engineering, Kyoto University

• Tamaru Keikichi

  Department Of Communications And Computer Engineering Kyoto University

• Hashimoto M

  Kyoto Univ. Kyoto‐shi Jpn

• Hashimoto Masanori

  Department Of Communications And Computer Engineering Kyoto University

• Hashimoto Masanori

  Department Of Breast And Endocrine Surgery University Of Tokyo

• Onodera Hidetoshi

  Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan

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