Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• Spatial power/ground level variation causes power/ground level mismatch between driver and receiver, and the mismatch affects gate propagation delay. This paper proposes a timing analysis method based on a concept called "PG level equalization" which is compatible with conventional STA frameworks. We equalize the power/ground levels of driver and receiver. The charging/discharging current variation due to equalization is compensated by replacing output load. We present an implementation method of the proposed concept, and demonstrate that the proposed method works well for multiple-input gates and RC load model.

• 社団法人電子情報通信学会の論文
• 2007-12-01

著者

• 小野寺 秀俊

  京都大学工学部電子工学科

• Onodera Hidetoshi

  Department of Communications and Computer Engineering, Kyoto University

• Onodera H

  Kyoto Univ. Kyoto‐shi Jpn

• Onodera Hidetoshi

  Kyoto Univ. Kyoto‐shi Jpn

• Onodera Hidetoshi

  Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit

• HASHIMOTO Masanori

  Department of Information Systems Engineering, Osaka University

• 小野寺 秀俊

  滋賀県立大学工学部

• Onodera Hidetoshi

  Department Of Communications And Computer Engineering Kyoto University

• YAMAGUCHI Junji

  Department of Communications and Computer Engineering, Kyoto University

• 小野寺 秀俊

  京都大学大学院工学研究科電子通信工学専攻

• Yamaguchi Junji

  Department Of Communications And Computer Engineering Kyoto University

• Hashimoto Masanori

  Osaka Univ. Suita‐shi Jpn

• Hashimoto Masanori

  Department Of Communications And Computer Engineering Kyoto University

• Yamaguchi Junji

  Department Of Bacteriology Kinki University School Of Medicine

• Hashimoto Masanori

  Department Of Breast And Endocrine Surgery University Of Tokyo

• 小野寺 秀俊

  京都大学情報学研究科通信情報システム専攻:京都大学光・電子理工学教育研究センター

• Onodera Hidetoshi

  Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan

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