Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling(<Special Section>Analog Circuits and Related SoC Integration Technologies)

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概要

• 論文の詳細を見る

• This paper discusses the resistive termination of on-chip high-performance interconnects. Resistive termination is effective to improve the bandwidth of on-chip interconnects, on the other hands, increases the power dissipation and the area. Therefore trade-off analysis about resistive termination is necessary. This paper proposes a method to determine the termination of on-chip interconnects. The termination derived by the proposed method provides minimum sensitivity to process variation as well as maximum eye-opening in voltage.

• 社団法人電子情報通信学会の論文
• 2007-06-01

著者

• 小野寺 秀俊

  京都大学工学部電子工学科

• Tsuchiya Akira

  Department of Communications and Computer Engineering, Kyoto University

• Onodera Hidetoshi

  Department of Communications and Computer Engineering, Kyoto University

• Onodera H

  Kyoto Univ. Kyoto‐shi Jpn

• Onodera Hidetoshi

  Kyoto Univ. Kyoto‐shi Jpn

• Onodera Hidetoshi

  Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit

• Tsuchiya Akira

  Kyoto Univ. Kyoto‐shi Jpn

• HASHIMOTO Masanori

  Department of Information Systems Engineering, Osaka University

• 小野寺 秀俊

  滋賀県立大学工学部

• Tsuchiya Akira

  Department Of Communications And Computer Engineering Kyoto University

• 小野寺 秀俊

  京都大学大学院工学研究科電子通信工学専攻

• Hashimoto Masanori

  Renesas Technology Corp.

• Hashimoto Masanori

  Department Of Communications And Computer Engineering Kyoto University

• Hashimoto Masanori

  Department Of Breast And Endocrine Surgery University Of Tokyo

• 小野寺 秀俊

  京都大学情報学研究科通信情報システム専攻:京都大学光・電子理工学教育研究センター

• Onodera Hidetoshi

  Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan

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