A Comprehensive Simulation and Test Environment for Prototype VLSI Verification(Verification)(<Special Section>Test and Verification of VLSI)
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概要
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This paper describes a comprehensive simulation and test environment for prototype LSI verification. We develop a Perl package, ST, for simulation & test of digital circuits. A designer can describe a testbench with the Perl syntax, which can be converted to various kinds of simulators and LSI testers. Parameters such as a target simulator/tester, cycle time and voltage levels can be changed very easily just modifying arguments of subroutines. We also develop OUT boards which consist of a tester-dependent mother board and a package-dependent daughter board. Using ST and the DUT boards, a designer can start verification just after getting fabricated LSIs.
- 社団法人電子情報通信学会の論文
- 2004-03-01
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