A 90nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations(Digital,<Special Section>Low-Power, High-Speed LSIs and Related Technologies)

スポンサーリンク

概要

• 論文の詳細を見る

• In this paper, we show that speed and yield of reconfigurable devices can be enhanced by utilizing within-die (WID) delay variations. An LUT Array LSI is fabricated to confirm whether FPGAs have clear WID variations to be utilized. We can measure delay variations by counting the number of LUTs a signal propagates within a certain time. Clear die-to-die (D2D) and WID variations are observed. We propose a variation model from the measurement results. Adequacy of the model is discussed from randomness of the random component. Effect of the speed and yield enhancement is confirmed using the proposed model. Yield increases from 80.0% to 100.0% by optimizing configurations.

• 社団法人電子情報通信学会の論文
• 2007-04-01

著者

• 小野寺 秀俊

  京都大学工学部電子工学科

• Onodera Hidetoshi

  Department of Communications and Computer Engineering, Kyoto University

• Onodera H

  Kyoto Univ. Kyoto‐shi Jpn

• Onodera Hidetoshi

  Kyoto Univ. Kyoto‐shi Jpn

• Onodera Hidetoshi

  Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit

• 小野寺 秀俊

  滋賀県立大学工学部

• Kobayashi Kazutoshi

  Kyoto Univ. Kyoto‐shi Jpn

• Katsuki Kazuya

  Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit

• KOBAYASHI Kazutoshi

  Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto Univers

• KOTANI Manabu

  Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto Univers

• 小野寺 秀俊

  京都大学大学院工学研究科電子通信工学専攻

• Kotani Manabu

  Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit

• 小野寺 秀俊

  京都大学情報学研究科通信情報システム専攻:京都大学光・電子理工学教育研究センター

• Onodera Hidetoshi

  Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan

• Kobayashi Kazutoshi

  Department of Applied Chemistry, Faculty of Science, Science University of Tokyo

関連論文

• Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells
• パネル討論 : 設計/CAD技術はディープサブミクロン時代の挑戦に耐えられるか
• CMOS論理ゲートにおける貫通電流による消費電力の定式化
• 抵抗アレイモデルを用いたアナログ回路用概略配線
• 形状最適化コンパクション
• ビルディングブロックレイアウトのための分枝限定配置手法
• ばらつき考慮設計に向けて(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
• ばらつき考慮設計に向けて(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
• Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells
• 基板バイポーラ効果によるSEUとMCUの発生機構の検討(製造性考慮設計,システムオンシリコンを支える設計技術)
• C-12-56 ω_nドメイン設計手法によるCDR-ICの低ジッタ化(C-12.集積回路,一般セッション)
• Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling(Analog Circuits and Related SoC Integration Technologies)
• Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line(Interconnect,VLSI Design and CAD Algorithms)
• Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
• Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
• Representative Frequency for Interconnect R(f)L(f)C Extraction(Parasitics and Noise)(VLSI Design and CAD Algorithms)
• Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
• C-12-27 Development of Design Process for RF MOSFET Model in the Future Technology
• PA-1 大学の研究をどのように産業界に活かすか?
• モデル依存性の小さいMOSFETパラメータ抽出システムの実現
• 相互結合インダクタを用いたTIA帯域向上手法(若手研究会)
• AI-1-3 ディペンダブルVLSIプラットフォームへの挑戦(AI-1.デイベンダブルVLSIに向けて,依頼シンポジウム,ソサイエティ企画)
• A 90nm 48×48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations(Low-Power and High-Performance VLSI Circuit Technology,VLSI Technology toward Frontiers of New Market)
• A 90nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
• A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era(Digital, Low-Power LSI and Low-Power IP)
• Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver(Analog Circuits and Related SoC Integration Technologies)
• A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era(Electronic Circuits)
• Experimental Study on Cell-Base High-Performance Datapath Design(IP Design)(VLSI Design and CAD Algorithms)
• Experimental Study on Cell-Base High-Performance Datapath Design
• Variable RF Inductor on Si CMOS Chip
• Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,VLSI Design and CAD Algorithms)
• 不確定パラメタの導入によるアナログ回路設計手順の再利用率向上手法
• A-58 モデル依存性の小さいMOSFETパラメータ抽出システムの実現(A-3. VLSI設計技術,一般講演)
• モデル依存性の小さいMOSFETパラメータ抽出手法
• アナログ回路設計手順の保存・再利用化手法
• Special Section on VLSI Design and CAD Algorithms
• Manufacturability-Aware Design of Standard Cells(Physical Design,VLSI Design and CAD Algorithms)
• Special Section on Analog Circuit Techniques for System-on-Chip Integration
• FOREWORD (Special Section on Analog Technologies in Submicron Era)
• デザインルールチェック並列処理化の一手法 : 並列スケジューリングによる手順割り当て
• デザインルールチェック並列処理化の一手法 : 並列スケジューリングによる手順割り当て
• 中間モデルを用いたモデル依存性の小さいMOSFETパラメータ抽出手法
• Statistical Gate Delay Model for Multiple Input Switching
• Timing Analysis Considering Temporal Supply Voltage Fluctuation
• Successive Pad Assignment for Minimizing Supply Voltage Drop(Power/Ground Network, VLSI Design and CAD Algorithms)
• An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
• 特集「システムLSI設計とその技術」の編集にあたって
• アナログ/ディジタル混載LSIのCAD技術
• BPBP型FMPPを用いたプロセッサボードの設計
• Model-Adaptable Parameter Extraction System for MOSFET Models
• Development of Module Generators from Extracted Design Procedures : Application to Analog Device Generation
• A-3-13 SystemC を用いたハードウェア・ソフトウェア設計 : SystemC のRTL記述からHDLへの変換
• A-3-12 SystemC を用いたハードウェア・ソフトウェア強調設計
• Architecture and Performance Evaluation of a New Functional Memory : Functional Memory for Addition (Special Section on VLSI Design and CAD Algorithms)
• A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization (Special Section on VLSI for Digital Signal Processing)
• An LSI for Low Bit-Rate Image Compression Using Vector Quantization(Special Issue on Multimedia, Network, and DRAM LSIs)
• A Memory-Based Parallel Processor for Vector Quantization:FMPP-VQ (Special Issue on New Concept Device and Novel Architecture LSIs)
• A Current Mode Cyclic A/D Converter with Submicron Processes (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
• A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture (Special Issue on New Architecture LSIs)
• A Comprehensive Simulation and Test Environment for Prototype VLSI Verification(Verification)(Test and Verification of VLSI)
• Crosstalk Noise Estimation for Generic RC Trees(Parasitics and Noise)(VLSI Design and CAD Algorithms)
• Effects of On-Chip Inductance on Power Distribution Grid(VLSI Design and CAD Algorithms)
• Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence
• Layout Dependent Matching Analysis of CMOS Circuits (Special Section on Analog Circuit Techniques and Related Topics)
• Increase in Delay Uncertainty by Performance Optimization(Special Section on VLSI Design and CAD Algorithms)
• Statistical Analysis of Clock Skew Variation in H-Tree Structure(Prediction and Analysis, VLSI Design and CAD Algorithms)
• Crosstalk Noise Optimization by Post-Layout Transistor Sizing(Physical Design)(VLSI Design and CAD Algorithms)
• Statistical Gate-Delay Modeling with Intra-Gate Variability(Parasitics and Noise)(VLSI Design and CAD Algorithms)
• A Performance Prediction of Clock Generation PLLs : A Ring Oscillator Based PLL and an LC Oscillator Based PLL(Integrated Electronics)
• FOREWORD (Special Issue on Synthesis and Verification of Hardware Design)
• A Hierarchical Statistical Optimization Method Driven by Constraint Generation Based on Mahalanobis' Distance(Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
• A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits
• Micro-Loading効果を考慮したCMOS回路の比精度解析
• レイアウトを考慮したCMOS回路の比精度解析
• A 65 nm Complementary Metal--Oxide--Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit
• Development of procedure for modeling MOSFET compatible with ITRS: noise and 1-5 characteristics modeling for RF/analog MOSFET (集積回路)
• More Mooreに立ちはだかるCMOSばらつきの理解に向けて(低電力設計,システムオンシリコンを支える設計技術)
• Multicore Large-Scale Integration Lifetime Extension by Negative Bias Temperature Instability Recovery-Based Self-Healing (Special Issue : Solid State Devices and Materials (2))
• ビット並列ブロック並列型FMPPにおける機能メモリのテスト方法
• ビット並列ブロック並列型FMPPアーキテクチャをとるプロトタイプLSIチップの概要
• ビット並列ブロック並列方式による機能メモリ型並列プロセッサの設計
• C-12-46 完全差動回路構成GVCOの高速化設計(C-12.集積回路,一般セッション)
• C-12-25 On-chip Monitor Circuits to Estimate Global Variations of Threshold Voltage and Gate Length
• Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System
• Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures
• Variable RF Inductor on Si CMOS Chip
• Impact of Body-Biasing Technique on Random Telegraph Noise Induced Delay Fluctuation
• Statistical Parameter Extraction for Intra- and Inter-Chip Variabilities of Metal–Oxide–Semiconductor Field-Effect Transistor Characteristics
• A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect
• On-Chip Detection of Process Shift and Process Spread for Post-Silicon Diagnosis and Model-Hardware Correlation
• ESR studies of the adsorption behavior of polystyrene at the solid-liquid interface.
• ESR studies of the competitive adsorption behavior of poly(methyl methacrylate) and polystyrene mixtures at the solid-liquid interface.
• Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation
• ESR studies of the adsorption behavior of styrene-methyl methacrylate copolymer at the solid-liquid interface.
• Adsorption of poly(methyl methacrylate) on silica surfaces having various silanol densities.

もっと見る 閉じる

スポンサーリンク