Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow.

• 社団法人電子情報通信学会の論文
• 2006-12-01

著者

• 小野寺 秀俊

  京都大学工学部電子工学科

• Tsuchiya Akira

  Department of Communications and Computer Engineering, Kyoto University

• Onodera H

  Kyoto Univ. Kyoto‐shi Jpn

• Onodera Hidetoshi

  Kyoto Univ. Kyoto‐shi Jpn

• Tsuchiya Akira

  Kyoto Univ. Kyoto‐shi Jpn

• HASHIMOTO Masanori

  Department of Information Systems Engineering, Osaka University

• KANAMOTO Toshiki

  Renesas Technology Corporation

• IKEDA Tatsuhiko

  Renesas Technology Corporation

• HASHIMOTO Masanori

  Osaka University

• 小野寺 秀俊

  滋賀県立大学工学部

• 小野寺 秀俊

  京都大学大学院工学研究科電子通信工学専攻

• Hashimoto Masanori

  Renesas Technology Corp.

• Hashimoto Masanori

  Osaka Univ. Suita‐shi Jpn

• Kanamoto Toshiki

  Renesas Design Corp.

• Kanamoto Toshiki

  Renesas Technology Corporation:osaka University

• Tsuchiya Akira

  Kyoto Univ. Kyoto Jpn

• Hashimoto Masanori

  Osaka Univ.

• 小野寺 秀俊

  京都大学情報学研究科通信情報システム専攻:京都大学光・電子理工学教育研究センター

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