Tsuchiya Akira | Kyoto Univ. Kyoto‐shi Jpn

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概要

• TSUCHIYA Akiraの詳細を見る
• 同名の論文著者
• Kyoto Univ. Kyoto‐shi Jpnの論文著者

関連著者

• 小野寺 秀俊

  京都大学工学部電子工学科

• Tsuchiya Akira

  Department of Communications and Computer Engineering, Kyoto University

• Onodera H

  Kyoto Univ. Kyoto‐shi Jpn

• Onodera Hidetoshi

  Kyoto Univ. Kyoto‐shi Jpn

• Tsuchiya Akira

  Kyoto Univ. Kyoto‐shi Jpn

• HASHIMOTO Masanori

  Department of Information Systems Engineering, Osaka University

• 小野寺 秀俊

  滋賀県立大学工学部

• 小野寺 秀俊

  京都大学大学院工学研究科電子通信工学専攻

• Hashimoto Masanori

  Renesas Technology Corp.

• Onodera Hidetoshi

  Department of Communications and Computer Engineering, Kyoto University

• Onodera Hidetoshi

  Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit

• Tsuchiya Akira

  Department Of Communications And Computer Engineering Kyoto University

• Onodera Hidetoshi

  Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan

• Hashimoto Masanori

  Department Of Communications And Computer Engineering Kyoto University

• Hashimoto Masanori

  Department Of Breast And Endocrine Surgery University Of Tokyo

• 小野寺 秀俊

  京都大学情報学研究科通信情報システム専攻:京都大学光・電子理工学教育研究センター

• KANAMOTO Toshiki

  Renesas Technology Corporation

• IKEDA Tatsuhiko

  Renesas Technology Corporation

• HASHIMOTO Masanori

  Osaka University

• HASHIMOTO Masanori

  PRESTO, JST

• Hashimoto Masanori

  Osaka Univ. Suita‐shi Jpn

• Kanamoto Toshiki

  Renesas Design Corp.

• Kanamoto Toshiki

  Renesas Technology Corporation:osaka University

• Tsuchiya Akira

  Kyoto Univ. Kyoto Jpn

• Hashimoto Masanori

  Osaka Univ.

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著作論文

• Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling(Analog Circuits and Related SoC Integration Technologies)
• Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line(Interconnect,VLSI Design and CAD Algorithms)
• Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
• Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
• Representative Frequency for Interconnect R(f)L(f)C Extraction(Parasitics and Noise)(VLSI Design and CAD Algorithms)

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