Tsuchiya Akira | Kyoto Univ. Kyoto‐shi Jpn
スポンサーリンク
概要
関連著者
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小野寺 秀俊
京都大学工学部電子工学科
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Tsuchiya Akira
Department of Communications and Computer Engineering, Kyoto University
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Onodera H
Kyoto Univ. Kyoto‐shi Jpn
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Onodera Hidetoshi
Kyoto Univ. Kyoto‐shi Jpn
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Tsuchiya Akira
Kyoto Univ. Kyoto‐shi Jpn
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HASHIMOTO Masanori
Department of Information Systems Engineering, Osaka University
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小野寺 秀俊
滋賀県立大学工学部
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小野寺 秀俊
京都大学大学院工学研究科電子通信工学専攻
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Hashimoto Masanori
Renesas Technology Corp.
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Onodera Hidetoshi
Department of Communications and Computer Engineering, Kyoto University
著作論文
- Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling(Analog Circuits and Related SoC Integration Technologies)
- Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line(Interconnect,VLSI Design and CAD Algorithms)
- Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
- Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- Representative Frequency for Interconnect R(f)L(f)C Extraction(Parasitics and Noise)(VLSI Design and CAD Algorithms)