Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling(<Special Section>Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
スポンサーリンク
概要
- 論文の詳細を見る
This paper discusses performance limitation of on-chip interconnects. On-chip global interconnects are considered to be a bottleneck of high-performance LSIs. To overcome this issue, high-speed signaling and large throughput interconnection using electrical wires have been studied. However the limitation of on-chip interconnects has not been examined sufficiently. This paper reveals the maximum performance of on-chip global interconnects based on derived analytic expressions and detailed circuit simulation. We derive trade-off curves among bit rate, interconnect length, and eye opening both for single-end and for differential signaling. The results show that differential signaling improves signaling performance several times compared with conventional single-end signaling, and demonstrate that 80 Gbps differential signaling on 10 mm interconnects is promising.
- 社団法人電子情報通信学会の論文
- 2005-04-01
著者
-
小野寺 秀俊
京都大学工学部電子工学科
-
Tsuchiya Akira
Department of Communications and Computer Engineering, Kyoto University
-
Onodera Hidetoshi
Department of Communications and Computer Engineering, Kyoto University
-
Onodera H
Kyoto Univ. Kyoto‐shi Jpn
-
Onodera Hidetoshi
Kyoto Univ. Kyoto‐shi Jpn
-
Onodera Hidetoshi
Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit
-
Tsuchiya Akira
Kyoto Univ. Kyoto‐shi Jpn
-
HASHIMOTO Masanori
Department of Information Systems Engineering, Osaka University
-
小野寺 秀俊
滋賀県立大学工学部
-
Tsuchiya Akira
Department Of Communications And Computer Engineering Kyoto University
-
小野寺 秀俊
京都大学大学院工学研究科電子通信工学専攻
-
Hashimoto Masanori
Renesas Technology Corp.
-
Hashimoto Masanori
Department Of Communications And Computer Engineering Kyoto University
-
Hashimoto Masanori
Department Of Breast And Endocrine Surgery University Of Tokyo
-
Onodera Hidetoshi
Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan
関連論文
- Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells
- パネル討論 : 設計/CAD技術はディープサブミクロン時代の挑戦に耐えられるか
- CMOS論理ゲートにおける貫通電流による消費電力の定式化
- 抵抗アレイモデルを用いたアナログ回路用概略配線
- 形状最適化コンパクション
- ビルディングブロックレイアウトのための分枝限定配置手法
- ばらつき考慮設計に向けて(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
- ばらつき考慮設計に向けて(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
- Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells
- 基板バイポーラ効果によるSEUとMCUの発生機構の検討(製造性考慮設計,システムオンシリコンを支える設計技術)
- C-12-56 ω_nドメイン設計手法によるCDR-ICの低ジッタ化(C-12.集積回路,一般セッション)
- Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling(Analog Circuits and Related SoC Integration Technologies)
- Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line(Interconnect,VLSI Design and CAD Algorithms)
- Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
- Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- Representative Frequency for Interconnect R(f)L(f)C Extraction(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- C-12-27 Development of Design Process for RF MOSFET Model in the Future Technology
- PA-1 大学の研究をどのように産業界に活かすか?
- モデル依存性の小さいMOSFETパラメータ抽出システムの実現
- 相互結合インダクタを用いたTIA帯域向上手法(若手研究会)
- AI-1-3 ディペンダブルVLSIプラットフォームへの挑戦(AI-1.デイベンダブルVLSIに向けて,依頼シンポジウム,ソサイエティ企画)
- A 90nm 48×48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations(Low-Power and High-Performance VLSI Circuit Technology,VLSI Technology toward Frontiers of New Market)
- A 90nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
- Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver(Analog Circuits and Related SoC Integration Technologies)
- A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era(Electronic Circuits)
- Experimental Study on Cell-Base High-Performance Datapath Design(IP Design)(VLSI Design and CAD Algorithms)
- Experimental Study on Cell-Base High-Performance Datapath Design
- Variable RF Inductor on Si CMOS Chip
- Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,VLSI Design and CAD Algorithms)
- 不確定パラメタの導入によるアナログ回路設計手順の再利用率向上手法
- A-58 モデル依存性の小さいMOSFETパラメータ抽出システムの実現(A-3. VLSI設計技術,一般講演)
- モデル依存性の小さいMOSFETパラメータ抽出手法
- アナログ回路設計手順の保存・再利用化手法
- Special Section on VLSI Design and CAD Algorithms
- Manufacturability-Aware Design of Standard Cells(Physical Design,VLSI Design and CAD Algorithms)
- Special Section on Analog Circuit Techniques for System-on-Chip Integration
- FOREWORD (Special Section on Analog Technologies in Submicron Era)
- Unruptured pseudoaneurysm of the cystic artery with acute calculous cholecystitis incidentally detected by computed tomography
- デザインルールチェック並列処理化の一手法 : 並列スケジューリングによる手順割り当て
- デザインルールチェック並列処理化の一手法 : 並列スケジューリングによる手順割り当て
- In Vitro Durability of One-bottle Resin Adhesives Bonded to Dentin
- 中間モデルを用いたモデル依存性の小さいMOSFETパラメータ抽出手法
- Development of the Cavernous Sinus in the Fetal Period : A Morphological Study
- Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration
- Statistical Gate Delay Model for Multiple Input Switching
- Timing Analysis Considering Temporal Supply Voltage Fluctuation
- Successive Pad Assignment for Minimizing Supply Voltage Drop(Power/Ground Network, VLSI Design and CAD Algorithms)
- An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
- Prediction of Self-Heating in Short Intra-Block Wires
- Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
- 特集「システムLSI設計とその技術」の編集にあたって
- アナログ/ディジタル混載LSIのCAD技術
- BPBP型FMPPを用いたプロセッサボードの設計
- Model-Adaptable Parameter Extraction System for MOSFET Models
- Development of Module Generators from Extracted Design Procedures : Application to Analog Device Generation
- Spontaneous Rupture of the Intrahepatic Bile Duct due to Carcinoma of the Ampulla of Vater: A Case Report
- Transistor Sizing of LCD Driver Circuit for Technology Migration(Circuit Synthesis,VLSI Design and CAD Algorithms)
- A-3-13 SystemC を用いたハードウェア・ソフトウェア設計 : SystemC のRTL記述からHDLへの変換
- A-3-12 SystemC を用いたハードウェア・ソフトウェア強調設計
- Architecture and Performance Evaluation of a New Functional Memory : Functional Memory for Addition (Special Section on VLSI Design and CAD Algorithms)
- A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization (Special Section on VLSI for Digital Signal Processing)
- An LSI for Low Bit-Rate Image Compression Using Vector Quantization(Special Issue on Multimedia, Network, and DRAM LSIs)
- A Memory-Based Parallel Processor for Vector Quantization:FMPP-VQ (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Current Mode Cyclic A/D Converter with Submicron Processes (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
- A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture (Special Issue on New Architecture LSIs)
- A Comprehensive Simulation and Test Environment for Prototype VLSI Verification(Verification)(Test and Verification of VLSI)
- Crosstalk Noise Estimation for Generic RC Trees(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- Effects of On-Chip Inductance on Power Distribution Grid(VLSI Design and CAD Algorithms)
- Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence
- Layout Dependent Matching Analysis of CMOS Circuits (Special Section on Analog Circuit Techniques and Related Topics)
- Increase in Delay Uncertainty by Performance Optimization(Special Section on VLSI Design and CAD Algorithms)
- Statistical Analysis of Clock Skew Variation in H-Tree Structure(Prediction and Analysis, VLSI Design and CAD Algorithms)
- Crosstalk Noise Optimization by Post-Layout Transistor Sizing(Physical Design)(VLSI Design and CAD Algorithms)
- Statistical Gate-Delay Modeling with Intra-Gate Variability(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- A Performance Prediction of Clock Generation PLLs : A Ring Oscillator Based PLL and an LC Oscillator Based PLL(Integrated Electronics)
- FOREWORD (Special Issue on Synthesis and Verification of Hardware Design)
- A Hierarchical Statistical Optimization Method Driven by Constraint Generation Based on Mahalanobis' Distance(Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
- A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits
- Diabetic Mastopathy in an Advanced Elderly Woman with Insulin-Dependent Type 2 Diabetes Mellitus
- Extragonadal germ cell tumor of the prostate associated with Klinefelter's syndrome
- Micro-Loading効果を考慮したCMOS回路の比精度解析
- レイアウトを考慮したCMOS回路の比精度解析
- Repeated Intracerebral Hemorrhage Associated with Impaired Platelet Aggregation : Report of Two Cases
- Surgical Treatment of Endolymphatic Sac Tumor With Adjunctive Stereotactic Radiation Therapy-Case Report-
- Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
- An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability
- Cellular response to dentin-bonding composite resins with dentin disks using the agar overlay method
- Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution
- Development of procedure for modeling MOSFET compatible with ITRS: noise and 1-5 characteristics modeling for RF/analog MOSFET (集積回路)
- More Mooreに立ちはだかるCMOSばらつきの理解に向けて(低電力設計,システムオンシリコンを支える設計技術)
- ビット並列ブロック並列型FMPPにおける機能メモリのテスト方法
- ビット並列ブロック並列型FMPPアーキテクチャをとるプロトタイプLSIチップの概要
- ビット並列ブロック並列方式による機能メモリ型並列プロセッサの設計
- C-12-46 完全差動回路構成GVCOの高速化設計(C-12.集積回路,一般セッション)
- C-12-25 On-chip Monitor Circuits to Estimate Global Variations of Threshold Voltage and Gate Length
- Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System
- Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures
- Variable RF Inductor on Si CMOS Chip
- A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect