Statistical Analysis of Clock Skew Variation in H-Tree Structure(Prediction and Analysis, <Special Section>VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that controls clock skew and power dissipation. In this paper, we evaluate clock skew under several variability models, and demonstrate relationship among clock skew, transition time constraint and power dissipation. Experimental results show that constraint of small transition time reduces clock skew under manufacturing and supply voltage variabilities, whereas there is an optimum constraint value for temperature gradient. Our experiments in a 0.18μm technology indicate that clock skew is minimized when clock buffer is sized such that the ratio of output and input capacitance is four.
- 社団法人電子情報通信学会の論文
- 2005-12-01
著者
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Onodera Hidetoshi
Department of Communications and Computer Engineering, Kyoto University
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Onodera Hidetoshi
Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit
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YAMAMOTO Tomonori
Department of Cardiovascular Surgery, Nihon University School of medicine
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HASHIMOTO Masanori
Department of Information Systems Engineering, Osaka University
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Onodera Hidetoshi
Department Of Communications And Computer Engineering Kyoto University
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Yamamoto Tomonori
Department Of Communications And Computer Engineering Kyoto University
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Yamamoto Tomonori
Department Of Biological Science And Technology Science University Of Tokyo
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Hashimoto Masanori
Osaka Univ. Suita‐shi Jpn
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Hashimoto Masanori
Department Of Communications And Computer Engineering Kyoto University
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Hashimoto Masanori
Department Of Breast And Endocrine Surgery University Of Tokyo
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Onodera Hidetoshi
Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan
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