Effects of On-Chip Inductance on Power Distribution Grid(<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We perform a case study work that evaluates relation between decoupling capacitance position and noise suppression effect, and we reveal that placing decoupling capacitance close to current load is necessary for noise reduction. We experimentally show that impact of on-chip inductance becomes small when on-chip decoupling capacitance is well placed according to local power consumption. We also examine influences of grid pitch, wire area, and spacing between paired power and ground wires on power supply noise. When effect of on-chip inductance on power/ground noise is significant, minification of grid pitch is more efficient than increase in wire area, and small spacing reduces power noise as we expected.

• 社団法人電子情報通信学会の論文
• 2005-12-01

著者

• Onodera Hidetoshi

  Department of Communications and Computer Engineering, Kyoto University

• Onodera Hidetoshi

  Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit

• HASHIMOTO Masanori

  Department of Information Systems Engineering, Osaka University

• Onodera Hidetoshi

  Department Of Communications And Computer Engineering Kyoto University

• Muramatsu Atsushi

  Department Of Communications And Computer Engineering Kyoto University

• Hashimoto Masanori

  Department Of Communications And Computer Engineering Kyoto University

• Hashimoto Masanori

  Department Of Communications And Computer Engineering Kyoto University:(present Address)department O

• Hashimoto Masanori

  Department Of Breast And Endocrine Surgery University Of Tokyo

• Onodera Hidetoshi

  Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan

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