Onodera Hidetoshi | Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit

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概要

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著作論文

Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling(Analog Circuits and Related SoC Integration Technologies)
Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line(Interconnect,VLSI Design and CAD Algorithms)
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Representative Frequency for Interconnect R(f)L(f)C Extraction(Parasitics and Noise)(VLSI Design and CAD Algorithms)
Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
C-12-27 Development of Design Process for RF MOSFET Model in the Future Technology
A 90nm 48×48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations(Low-Power and High-Performance VLSI Circuit Technology,VLSI Technology toward Frontiers of New Market)
A 90nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver(Analog Circuits and Related SoC Integration Technologies)
Experimental Study on Cell-Base High-Performance Datapath Design(IP Design)(VLSI Design and CAD Algorithms)
Experimental Study on Cell-Base High-Performance Datapath Design
Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,VLSI Design and CAD Algorithms)
Special Section on VLSI Design and CAD Algorithms
Manufacturability-Aware Design of Standard Cells(Physical Design,VLSI Design and CAD Algorithms)
Statistical Gate Delay Model for Multiple Input Switching
Timing Analysis Considering Temporal Supply Voltage Fluctuation
Successive Pad Assignment for Minimizing Supply Voltage Drop(Power/Ground Network, VLSI Design and CAD Algorithms)
An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
A Memory-Based Parallel Processor for Vector Quantization:FMPP-VQ (Special Issue on New Concept Device and Novel Architecture LSIs)
A Current Mode Cyclic A/D Converter with Submicron Processes (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
Crosstalk Noise Estimation for Generic RC Trees(Parasitics and Noise)(VLSI Design and CAD Algorithms)
Effects of On-Chip Inductance on Power Distribution Grid(VLSI Design and CAD Algorithms)
Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence
Layout Dependent Matching Analysis of CMOS Circuits (Special Section on Analog Circuit Techniques and Related Topics)
Increase in Delay Uncertainty by Performance Optimization(Special Section on VLSI Design and CAD Algorithms)
Statistical Analysis of Clock Skew Variation in H-Tree Structure(Prediction and Analysis, VLSI Design and CAD Algorithms)
Crosstalk Noise Optimization by Post-Layout Transistor Sizing(Physical Design)(VLSI Design and CAD Algorithms)
Statistical Gate-Delay Modeling with Intra-Gate Variability(Parasitics and Noise)(VLSI Design and CAD Algorithms)
A Performance Prediction of Clock Generation PLLs : A Ring Oscillator Based PLL and an LC Oscillator Based PLL(Integrated Electronics)
A Hierarchical Statistical Optimization Method Driven by Constraint Generation Based on Mahalanobis' Distance(Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits
Development of procedure for modeling MOSFET compatible with ITRS: noise and 1-5 characteristics modeling for RF/analog MOSFET (集積回路)
Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System
Variable RF Inductor on Si CMOS Chip

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