Okada Kenichi | Department Of Physical Electronics Tokyo Institute Of Technology

スポンサーリンク

概要

関連著者

もっと見る

著作論文

A Multi-Stage 60GHz CMOS LNA Using Dual Noise-Matching Technique
A De-Embedding Method Using Different-Length Transmission Lines for mm-Wave CMOS Device Modeling
Evaluation of a Multi-Line De-Embedding Technique up to 110GHz for Millimeter-Wave CMOS Circuit Design
Analysis of CMOS Transconductance Amplifiers for Sampling Mixers
Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators
Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators
A Wide-Tunable LC-Based Voltage-Controlled Oscillator Using a Divide-by-N Injection-Locked Frequency Divider
The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique
Ring Hydroxylations of Aromatic Amino Acid Derivatives and Toluene by Hydrogen Peroxide Catalyzed by Manganese Halogenated Porphyrins in CH_2Cl_2/H_2O and Lipid Bilayers
Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence
Layout Dependent Matching Analysis of CMOS Circuits (Special Section on Analog Circuit Techniques and Related Topics)
Statistical Gate-Delay Modeling with Intra-Gate Variability(Parasitics and Noise)(VLSI Design and CAD Algorithms)
Measurement of Integrated PA-to-LNA Isolation on Si CMOS Chip
Tunable CMOS Power Amplifiers for Reconfigurable Transceivers
Topology and Design Considerations of 60 GHz CMOS LNAs for Noise Performance Improving
Two-Stage Band-Selectable CMOS Power Amplifiers Using Inter-Stage Frequency Tuning
A Dual-Conduction Class-C VCO for a Low Supply Voltage
A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors
Evaluation of L-2L De-Embedding Method Considering Misalignment of Contact Position for Millimeter-Wave CMOS Circuit Design

もっと見る

スポンサーリンク