Tunable CMOS Power Amplifiers for Reconfigurable Transceivers
スポンサーリンク
概要
- 論文の詳細を見る
This paper presents three CMOS power amplifiers (PA) which realize wide-tunable output impedance matching. For realization of multi-standard and single-chip transceiver, the prototypes were fabricated by 0.18µm CMOS process. The proposed PAs can achieve a tunable impedance matching within a wide frequency range by utilizing a resistive feedback and parallel resonator with an inductor and capacitor array. Therefore, the proposed PA has a realization possibility of isolator-less PA which contributes to decrease die area including external component. In other words, the PAs have tunable impedance matching function at their output ends. With a 3.3-V supply, three power amplifiers can cover frequency ranges of 0.9-3.0GHz, 2.1-5.8GHz, and 5.7-9.7GHz, respectively. The PAs realize P1dB of 21dBm, Psat of 22dBm, and PAEpeak of larger than 23%. The proposed PAs present a potential to realize multi-band transceivers without isolators.
- 2011-11-01
著者
-
Imanishi Daisuke
Department Of Hematology And Molecular Medicine Unit Atomic Bomb Disease Institute Nagasaki Universi
-
Okada Kenichi
Department Of Physical Electronics Tokyo Institute Of Technology
-
Matsuzawa Akira
Department Of Physical Electronics Tokyo Institute Of Technology
-
Okada Kenichi
Department Of Communications And Computer Engineering Kyoto University
-
Matsuzawa Akira
Dep. Of Physical Electronics Tokyo Inst. Of Technol.
-
HONG JeeYoung
Department of Physical Electronics, Tokyo Institute of Technology
-
Matsuzawa Akira
Department Of Physical Electronics Graduate School Of Science And Engineering Tokyo Institute Of Technology
-
Hong Jeeyoung
Department Of Physical Electronics Tokyo Institute Of Technology
-
Imanishi Daisuke
Department Of Physical Electronics Tokyo Institute Of Technology
関連論文
- Comparative analysis of remission induction therapy for high-risk MDS and AML progressed from MDS in the MDS200 study of Japan Adult Leukemia Study Group
- Long-term efficacy of imatinib in a practical setting is correlated with imatinib trough concentration that is influenced by body size : a report by the Nagasaki CML Study Group
- Successful cord blood transplantation for mycosis fungoides.
- Imatinib Provides Durable Molecular and Cytogenetic Responses in a Practical Setting for Both Newly Diagnosed and Previously Treated Chronic Myelogenous Leukemia : A Study in Nagasaki Prefecture, Japan
- Human T cell leukemia virus type-1 Tax activates human macrophage inflammatory protein-3α/CCL20 gene transcription via the NF-kB pathway
- A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter(Analog Circuits and Related SoC Integration Technologies)
- Observation of One-dimensional Spinodal Decomposition in a Nematic Liquid Crystal(General)
- A Multi-Stage 60GHz CMOS LNA Using Dual Noise-Matching Technique
- A De-Embedding Method Using Different-Length Transmission Lines for mm-Wave CMOS Device Modeling
- Evaluation of a Multi-Line De-Embedding Technique up to 110GHz for Millimeter-Wave CMOS Circuit Design
- Analysis of CMOS Transconductance Amplifiers for Sampling Mixers
- Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators
- A Case of Intravascular Large B-cell Lymphoma (IVLBCL) with no Abnormal Findings on Chest Computed Tomography Diagnosed by Random Transbronchial Lung Biopsy
- Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators
- A Wide-Tunable LC-Based Voltage-Controlled Oscillator Using a Divide-by-N Injection-Locked Frequency Divider
- The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique
- Ring Hydroxylations of Aromatic Amino Acid Derivatives and Toluene by Hydrogen Peroxide Catalyzed by Manganese Halogenated Porphyrins in CH_2Cl_2/H_2O and Lipid Bilayers
- An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques
- A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing
- The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time(Analog Circuits and Related SoC Integration Technologies)
- Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence
- Layout Dependent Matching Analysis of CMOS Circuits (Special Section on Analog Circuit Techniques and Related Topics)
- Statistical Gate-Delay Modeling with Intra-Gate Variability(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- Design Challenges of Analog-to-Digital Converters in Nanoscale CMOS(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
- Analysis and Design of Direct Reference Feed-Forward Compensation for Fast-Settling All-Digital Phase-Locked Loop(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
- Compensation techniques for integrated analog device issues
- Wiring technology for analog and mixed signal LSIs
- Mixed Signal SoC Era(Analog Circuit and Device Technologies)
- Expression of myeloperoxidase and gene mutations in AML patients with normal karyotype: double CEBPA mutations are associated with high percentage of MPO positivity in leukemic blasts.
- Measurement of Integrated PA-to-LNA Isolation on Si CMOS Chip
- A 14.3% PAE parallel class-A and AB 60GHz CMOS PA
- Successful treatment of a chronic-phase T-315I-mutated chronic myelogenous leukemia patient with a combination of imatinib and interferon-alfa
- Tunable CMOS Power Amplifiers for Reconfigurable Transceivers
- Allogeneic hematopoietic stem cell transplantation for ATL with central nervous system involvement : The Nagasaki Transplant Group experience
- Topology and Design Considerations of 60 GHz CMOS LNAs for Noise Performance Improving
- Two-Stage Band-Selectable CMOS Power Amplifiers Using Inter-Stage Frequency Tuning
- A Dual-Conduction Class-C VCO for a Low Supply Voltage
- A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors
- Inter-Stage Tunable Notch Filter for a Multi-Band WCDMA Receiver
- A Wideband Common-Gate Low-Noise Amplifier Using Capacitive Feedback
- A 24dB Gain 51-68GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors
- An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator
- A 0.5-V, 0.05-to-3.2GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition
- Evaluation of L-2L De-Embedding Method Considering Misalignment of Contact Position for Millimeter-Wave CMOS Circuit Design
- A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching
- Statistical Parameter Extraction for Intra- and Inter-Chip Variabilities of Metal–Oxide–Semiconductor Field-Effect Transistor Characteristics
- C-12-11 Indutors and Transformers on 65 nm CMOS Technology for 60 GHz Applications
- Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers
- A 20GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60GHz Frequency Synthesizer
- A Low-Noise High-Dynamic Range Charge Sensitive Amplifier for Gas Particle Detector Pixel Readout LSIs
- A Study of Stability and Phase Noise of Tail Capacitive-Feedback VCOs
- Design of CMOS Low-Noise Analog Circuits for Particle Detector Pixel Readout LSIs
- A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells
- Evaluation of L-2L De-Embedding Method Considering Misalignment of Contact Position for Millimeter-Wave CMOS Circuit Design
- Ultra-Low-Voltage Dynamic Amplifier
- A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier
- C-12-32 A Current-Reuse Class-C VCO using Dynamic Start-up Circuits
- Feasibility of cord blood transplantation in chemosensitive adult T-cell leukemia/lymphoma : a retrospective analysis of the Nagasaki Transplantation Network