Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence
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概要
- 論文の詳細を見る
The main purpose of our method is to obtain realistic worst-case delay in statistical timing analyses. This paper proposes a method of statistical delay calculation based on measured intra-chip and inter-chip variabilities. We present a modeling and extracting method of transistor characteristics for the intra-chip variability and the inter-chip variability. In the modeling of the intra-chip variability, it is important to consider a gate-size dependence by which the amount of intra-chip variation is affected. This effect is not captured in a statistical delay analysis reported so far. Our method proposes a method for modeling of the device variability and statistical delay calculation with consideration of the size dependence, and uses a response surface method (RSM) to calculate a delay variation with low processing cost. We evaluate the accuracy of our method, and we show some experimental results the variation of a circuit delay characterized by the measured variances of transistor currents.
- 社団法人電子情報通信学会の論文
- 2003-04-01
著者
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Onodera Hidetoshi
Department of Communications and Computer Engineering, Kyoto University
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Onodera Hidetoshi
Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit
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OKADA Kenichi
Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of T
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Okada Kenichi
Department Of Physical Electronics Tokyo Institute Of Technology
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Okada Kenichi
Department Of Communications And Computer Engineering Kyoto University
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