Manufacturability-Aware Design of Standard Cells(Physical Design,<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• We focus our attention on the layout dependent Across Chip Linewidth Variability (ACLV) of gate-forming poly-silicon patterns as a measure for manufacturability, which is a major contributor of systematic gate-length variation. First, we study the ACLV of standard cell layouts by lithography simulation. Then, we introduce regularity in gate-forming poly-silicon patterns and how it improves the ACLV and also how it incurs area-overhead. According to the investigation, we propose two design guidelines for standard-cell layout that can reduce ACLV with reasonable area overhead. Those guidelines include on-grid fixed-pitch layout with dummy-poly insertion and stretched gate-poly extension. Design experiments assuming a 65nm process technology indicate that a D-FF designed with the first guideline reduces ACLV by 35% with 14% area overhead and the second guideline reduces ACLV by 75% with 29% area overhead at the best focus condition. Under defocus conditions, both layouts exhibit stable characteristics whereas the variability of conventional layout grows rapidly as the level of defocus increases. Circuit-level lithography simulation over benchmark circuits also supports that the proposed guidelines considerably reduces the amount of gate length variation.

• 社団法人電子情報通信学会の論文
• 2007-12-01

著者

• Onodera Hidetoshi

  Department of Communications and Computer Engineering, Kyoto University

• Onodera Hidetoshi

  Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit

• MUTA Hirokazu

  Department of Communications and Computer Engineering, Kyoto University

• Muta Hirokazu

  Department Of Communications And Computer Engineering Kyoto University:(present Office)sony Corporat

• Muta Hirokazu

  Department Of Chemistry And Biotechnology Gradutate School Of Engineering The University Of Tokyo

• Onodera Hidetoshi

  Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan

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