Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver(<Special Section>Analog Circuits and Related SoC Integration Technologies)

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概要

• 論文の詳細を見る

• This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip transmission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5Gbps.

• 社団法人電子情報通信学会の論文
• 2007-06-01

著者

• 小野寺 秀俊

  京都大学工学部電子工学科

• Tsuchiya Akira

  Department of Communications and Computer Engineering, Kyoto University

• Onodera Hidetoshi

  Department of Communications and Computer Engineering, Kyoto University

• Onodera H

  Kyoto Univ. Kyoto‐shi Jpn

• Onodera Hidetoshi

  Kyoto Univ. Kyoto‐shi Jpn

• Onodera Hidetoshi

  Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit

• Tsuchiya Akira

  Department Of Communications And Computer Engineering Kyoto University

• Onodera Hidetoshi

  Department Of Communications And Computer Engineering Kyoto University

• KUBOKI Takeshi

  Department of Communications and Computer Engineering, Kyoto University

• Kuboki Takeshi

  Department Of Communications And Computer Engineering Kyoto University

• 小野寺 秀俊

  京都大学大学院工学研究科電子通信工学専攻

• 小野寺 秀俊

  京都大学情報学研究科通信情報システム専攻:京都大学光・電子理工学教育研究センター

• Onodera Hidetoshi

  Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan

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