Onodera Hidetoshi | Kyoto Univ. Kyoto‐shi Jpn

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概要

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著作論文

パネル討論 : 設計/CAD技術はディープサブミクロン時代の挑戦に耐えられるか
ばらつき考慮設計に向けて(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
ばらつき考慮設計に向けて(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
C-12-56 ω_nドメイン設計手法によるCDR-ICの低ジッタ化(C-12.集積回路,一般セッション)
Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling(Analog Circuits and Related SoC Integration Technologies)
Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line(Interconnect,VLSI Design and CAD Algorithms)
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Representative Frequency for Interconnect R(f)L(f)C Extraction(Parasitics and Noise)(VLSI Design and CAD Algorithms)
Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
PA-1 大学の研究をどのように産業界に活かすか?
AI-1-3 ディペンダブルVLSIプラットフォームへの挑戦(AI-1.デイベンダブルVLSIに向けて,依頼シンポジウム,ソサイエティ企画)
A 90nm 48×48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations(Low-Power and High-Performance VLSI Circuit Technology,VLSI Technology toward Frontiers of New Market)
A 90nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver(Analog Circuits and Related SoC Integration Technologies)
A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era(Electronic Circuits)
Experimental Study on Cell-Base High-Performance Datapath Design(IP Design)(VLSI Design and CAD Algorithms)
Experimental Study on Cell-Base High-Performance Datapath Design
Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,VLSI Design and CAD Algorithms)
Special Section on Analog Circuit Techniques for System-on-Chip Integration
FOREWORD (Special Section on Analog Technologies in Submicron Era)
Timing Analysis Considering Temporal Supply Voltage Fluctuation
Successive Pad Assignment for Minimizing Supply Voltage Drop(Power/Ground Network, VLSI Design and CAD Algorithms)
An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
特集「システムLSI設計とその技術」の編集にあたって
アナログ/ディジタル混載LSIのCAD技術
Model-Adaptable Parameter Extraction System for MOSFET Models
Development of Module Generators from Extracted Design Procedures : Application to Analog Device Generation
Architecture and Performance Evaluation of a New Functional Memory : Functional Memory for Addition (Special Section on VLSI Design and CAD Algorithms)
A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization (Special Section on VLSI for Digital Signal Processing)
An LSI for Low Bit-Rate Image Compression Using Vector Quantization(Special Issue on Multimedia, Network, and DRAM LSIs)
A Memory-Based Parallel Processor for Vector Quantization:FMPP-VQ (Special Issue on New Concept Device and Novel Architecture LSIs)
A Current Mode Cyclic A/D Converter with Submicron Processes (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture (Special Issue on New Architecture LSIs)
A Comprehensive Simulation and Test Environment for Prototype VLSI Verification(Verification)(Test and Verification of VLSI)
FOREWORD (Special Issue on Synthesis and Verification of Hardware Design)
Development of procedure for modeling MOSFET compatible with ITRS: noise and 1-5 characteristics modeling for RF/analog MOSFET (集積回路)
More Mooreに立ちはだかるCMOSばらつきの理解に向けて(低電力設計,システムオンシリコンを支える設計技術)
C-12-46 完全差動回路構成GVCOの高速化設計(C-12.集積回路,一般セッション)
C-12-25 On-chip Monitor Circuits to Estimate Global Variations of Threshold Voltage and Gate Length
Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures

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