Onodera Hidetoshi | The Department Of Communications And Computer Engineering Kyoto University

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著作論文

Design Optimization Methodology for On-Chip Spiral Inductors(Analog Circuit and Device Technologies)
Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect (Interface and Interconnect Techniques, VLSI Design Technology in the Sub-100nm Era)
Variability : Modeling and Its Impact on Design (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
An LSI for Low Bit-Rate Image Compression Using Vector Quantization(Special Issue on Multimedia, Network, and DRAM LSIs)
Statistical Modeling of Device Characteristics with Systematic Variability(Special Section on Analog Circuit Techniques Supporting the System LSI Era)
A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance(Special Section on VLSI Design and CAD Algorithms)
A Method for Linking Process-Level Variability to System Performances (Special Section on VLSI Design and CAD Algorithms)
Analytical Formulas of Output Waveform and Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC π Load
A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis (Special Section on VLSI Design and CAD Algorithms)
Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design(Special Section on VLSI Design and CAD Algorithms)

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