Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design(Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cell-based circuits as much as possible. Our method reduces power dissipation of detail-routed circuits while preserving interconnects. The effectiveness of our method is experimentally evaluated using 3 circuits. The power dissipation is reduced by 75% maximum and 60% on average without delay increase. Compared with discrete cell sizing, the proposed method reduces power dissipation furthermore by 30% on average.
- 一般社団法人電子情報通信学会の論文
- 2001-11-01
著者
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Onodera Hidetoshi
The Department Of Communications And Computer Engineering Kyoto University
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Hashimoto Masanori
The Department Of Communications And Computer Engineering Kyoto University
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Onodera Hidetoshi
The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive
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