A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis (Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
This paper discusses a gate resizing method for performance enhancement based on statistical static timing analysis. The proposed method focuses on timing uncertainties caused by local random fluctuation. Our method aims to remove both over-design and under-design of a circuit, and realize high-performance and high-reliability LSI design. The effectiveness of our method is examined by 6 benchmark circuits. We verify that our method can reduce the delay time further from the circuits optimized for minimizing the delay without the consideration of delay fluctuation.
- 一般社団法人電子情報通信学会の論文
- 2000-12-25
著者
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Onodera Hidetoshi
The Department Of Communications And Computer Engineering Kyoto University
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Hashimoto Masanori
The Department Of Communications And Computer Engineering Kyoto University
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Onodera Hidetoshi
The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive
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