A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance(Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• Abstract-Phase locked loop(PLL)is widely used for many purposes. The lock-up performance is one of the most important target items in designing PLLs. In a digital PLL, it is difficult to control the frequency and phase independently, which makes it difficult to improve lock-up performance. A variable delay circuit which adjusts only the phase of the PLL is introduced here. A full loop model simulation with measured controllable delay shows the effectiveness of applying the phase adjust method with the variable delay to the PLL.

• 2001-11-01

著者

• ONODERA Hidetoshi

  the Department of Communications and Computer Engineering, Kyoto University

• Fujita Hiroaki

  The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive

• Onodera Hidetoshi

  The Department Of Communications And Computer Engineering Kyoto University

• YASUDA Takeo

  the Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto Uni

• Yasuda Takeo

  The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive

• Onodera Hidetoshi

  The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive

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