Variability : Modeling and Its Impact on Design (Signal Integrity and Variability, <Special Section> VLSI Design Technology in the Sub-100nm Era)

スポンサーリンク

概要

• 論文の詳細を見る

• As the technology scaling approaching nano-scale region, variability in device performance becomes a major issue in the design of integrated circuits. Besides the growing amount of variability, the statistical nature of the variability is changing as the progress of technology generation. In the past, die-to-die variability, which is well managed by the worst case design technique, dominates over within-die variability. In present and the future, the amount of within-die variability is increasing and it casts a challenge in design methodology. This paper first shows measured results of variability in three different processes of 0.35, 0.18, and 0.13μm technologies, and explains the above mentioned trend of variability. An example of modeling for the within-die variability is explained. The impact of within-die random variability on circuit performance is demonstrated using a simple numerical example. It shows that a circuit that is designed optimally under the assumption of deterministic delay is now most susceptible to random fluctuation in delay, which clearly indicates the requirement of statistical design methodology.

• 社団法人電子情報通信学会の論文

著者

• ONODERA Hidetoshi

  the Department of Communications and Computer Engineering, Kyoto University

• Onodera Hidetoshi

  The Department Of Communications And Computer Engineering Kyoto University

• Onodera Hidetoshi

  The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive

関連論文

• Design Optimization Methodology for On-Chip Spiral Inductors(Analog Circuit and Device Technologies)
• Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect (Interface and Interconnect Techniques, VLSI Design Technology in the Sub-100nm Era)
• Variability : Modeling and Its Impact on Design (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
• An LSI for Low Bit-Rate Image Compression Using Vector Quantization(Special Issue on Multimedia, Network, and DRAM LSIs)
• Statistical Modeling of Device Characteristics with Systematic Variability(Special Section on Analog Circuit Techniques Supporting the System LSI Era)
• A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance(Special Section on VLSI Design and CAD Algorithms)
• A Method for Linking Process-Level Variability to System Performances (Special Section on VLSI Design and CAD Algorithms)
• Analytical Formulas of Output Waveform and Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC π Load
• A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis (Special Section on VLSI Design and CAD Algorithms)
• Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design(Special Section on VLSI Design and CAD Algorithms)

スポンサーリンク