Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect (Interface and Interconnect Techniques, <Special Section> VLSI Design Technology in the Sub-100nm Era)

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概要

• 論文の詳細を見る

• In this paper, we propose alternate self shielding to remove critical transitions of on-chip global interconnect. Our proposed method alternates shield and signal wires cycle by cycle. The conventional self-shielding methods need additional wires to remove critical transition by encoding. The proposed alternate self-shielding, however, requires no additional wires. We evaluate our method by simulating signal transimission with a circuit simulator. As a result, our proposed method is superior in bit rate compared to others from 10% to 75%.

• 社団法人電子情報通信学会の論文

著者

• ONODERA Hidetoshi

  the Department of Communications and Computer Engineering, Kyoto University

• Tsuchiya Akira

  The Department Of Communications And Computer Engineering Kyoto University

• Onodera Hidetoshi

  The Department Of Communications And Computer Engineering Kyoto University

• Kobayashi Kazutoshi

  The Department Of Communications And Computer Engineering Kyoto University

• YUYAMA Yoichi

  the Department of Communications and Computer Engineering, Kyoto University

• Yuyama Yoichi

  The Department Of Communications And Computer Engineering Kyoto University

• Onodera Hidetoshi

  The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive

関連論文

• Design Optimization Methodology for On-Chip Spiral Inductors(Analog Circuit and Device Technologies)
• Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect (Interface and Interconnect Techniques, VLSI Design Technology in the Sub-100nm Era)
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