Analytical Formulas of Output Waveform and Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC π Load

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概要

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• As MOSFET sizes and wire widths become very small in recent years, influence of resistive component of interconnects on the estimation of propagation delay and power dissipation can no longer be neglected. In this paper we present formulas of output waveform at driving point and short-circuit power dissipation for static CMOS logic gates driving a CRC π load. By representing the short-circuit current and the current flowing in the resistance of a CRC π load by piece-wise linear functions, a closed-form formula is derived. On the gate delay the error of our formula is less than 8% from SPICE in our experiments. These formulas will contribute to faster estimation of circuit speed and power dissipation of VLSI chips on timing level simulators.

• 社団法人電子情報通信学会の論文
• 1998-03-25

著者

• Onodera Hidetoshi

  The Department Of Communications And Computer Engineering Kyoto University

• TAMARU Keikichi

  the Department of Electronics and Communication, Graduate School of Engineering, Kyoto University

• Tamaru Keikichi

  The Department Of Electronics And Communications Kyoto University

• HARATA Akio

  the Department of Electronics and Communications, Kyoto University

• Harata Akio

  The Department Of Electronics And Communications Kyoto University

• Onodera Hidetoshi

  The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive

• Onodera Hidetoshi

  The Department Of Electronics And Communications Kyoto University

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