A Method for Linking Process-Level Variability to System Performances (Special Section on VLSI Design and CAD Algorithms)

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概要

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• In this paper we present a case study of a hierarchical statistical analysis. The method which we use here bridges the statistical information between process-level and system-level, and enables us to know the effect of the process variation on the system performance. We use two modeling techniques-intermediate model and response surface model-in order to link the statistical information between adjacent design levels. We show an experiment of the hierarchical statistical analysis applied to a Phase Locked Loop(PLL) circuit, and indicate that the hierarchical statistical analysis is practical with respect to both accuracy and simulation cost. Following three applications are also presented in order to show advantage of this linking method;these are Monte Carlo analysis, worst-case analysis, and sensitive analysis. The results of the Monte Carlo and the worst-case analysis indicate that this method is realistic statistical one. The result of the sensitive analysis enables us to evaluate the effect of process variation at the system level. Also, we can derive constraints on the process variation from a performance requirement.

• 2000-12-25

著者

• Onodera Hidetoshi

  The Department Of Communications And Computer Engineering Kyoto University

• Fujita T

  Kyoto Univ. Kyoto‐shi Jpn

• FUJITA Tomohiro

  the Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto Uni

• Onodera Hidetoshi

  The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive

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