Kobayashi K | Toyama Prefectural Univ. Toyama‐ken Jpn
スポンサーリンク
概要
関連著者
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Kobayashi K
Toyama Prefectural Univ. Toyama‐ken Jpn
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Kobayashi Kensuke
The Author Is With Lecroy Corp.
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Kobayashi K
The Author Is With Lecroy Corp.
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小野寺 秀俊
京都大学工学部電子工学科
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Onodera H
Kyoto Univ. Kyoto‐shi Jpn
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Onodera Hidetoshi
Kyoto Univ. Kyoto‐shi Jpn
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小野寺 秀俊
滋賀県立大学工学部
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小野寺 秀俊
京都大学大学院工学研究科電子通信工学専攻
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TAMARU Keikichi
Okayama University of Science
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Tamaru K
Okayama University Of Science
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Kobayashi Kazutoshi
Graduate School Of Informatics Kyoto University
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Onodera Hidetoshi
Graduate School Of Informatics Kyoto University
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Onodera Hidetoshi
Department of Communications and Computer Engineering, Kyoto University
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Onodera Hidetoshi
Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit
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Kobayashi Haruo
Department Of Electronic Engineering Faculty Of Engineering Gunma University
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Kobayashi Haruo
Sanyo Lsi Design-system Soft Co. Ltd.
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Kobayashi Kazutoshi
Vlsi Design And Education Center The University Of Tokyo
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Kobayashi K
Yamatake Corporation
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KIMURA Masaru
The author is with IWATSU Electric Co. Ltd.
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Kobayashi H
The Department Of Electronic Engineering Faculty Of Engineering Gunma University
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Kobayashi H
Sanyo Lsi Design-system Soft Co. Ltd.
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Kimura M
The Author Is With Iwatsu Electric Co. Ltd.
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Kobayashi K
Graduate School Of Informatics Kyoto University
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Higuchi Akihiko
Graduate School Of Informatics Kyoto University:(present Office)matsushita Electric Co. Ltd.
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Onodera Hidetoshi
Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan
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Yasuura Hiroto
Faculty Of Engineering Kyoto University
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KOBAYASHI Kazutoshi
Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto Univers
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HIGUCHI Akihiko
Graduate School of Informatics, Kyoto University
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HIGUCHI Akihiko
Department of Communications and Computer Engineering, Kyoto University
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KOBAYASHI Kazutoshi
VLSI Design and Education Center, The University of Tokyo
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ONODERA Hidetoshi
the Department of Communications and Computer Engineering, Kyoto University
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Kinoshita M
Kyoto Univ. Kyoto
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Kinoshita Masayoshi
Department Of Bioapplied Chemistry Faculty Of Engineering Osaka City University
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KOBAYASHI Kazutoshi
Faculty of Engineering, Kyushu University
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Onodera Hidetoshi
Faculty of Engineering, Kyoto University
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Tamaru Keikichi
Faculty of Engineering, Kyoto University
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Onodera Hidetoshi
Faculty Of Engineering Kyoto University
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Onodera Hidetoshi
The Department Of Communications And Computer Engineering Kyoto University
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Kobayashi Kazutoshi
The Department Of Communications And Computer Engineering Kyoto University
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Kobayashi Kazutoshi
Faculty Of Engineering Kyushu University
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YAMAOKA Masanao
Graduate School of Informatics, Kyoto University
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KOBAYASHI Yukifumi
Graduate School of Informatics, Kyoto University
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TERADA Kazuhiko
Graduate School of Informatics, Kyoto University
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TAMARU Keikichi
Graduate School of Informatics, Kyoto University
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NAKAMURA Noritsugu
the Department of Electronics and Communication, Graduate School of Engineering, Kyoto University
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TERADA Kazuhiko
the Department of Electronics and Communication, Graduate School of Engineering, Kyoto University
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TAMARU Keikichi
the Department of Electronics and Communication, Graduate School of Engineering, Kyoto University
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TAMARU Keikichi
Department of Electronics and Communication, Graduate School of Engineering, Kyoto University
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KOBAYASHI Haruo
The author is with the Department of Electronic Engineering, Gunma University
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KIMURA Masaru
Teratec Corporation, Research and Development
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MINEGISHI Atsushi
Teratec Corporation, Research and Development
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KOBAYASHI Kensuke
Teratec Corporation, Research and Development
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KOBAYASHI Haruo
Dept.of Electronic Engineering, Gunma University
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KAWABATA Yutaka
Computer and Network Systems Core, Kanazawa Institute of Technology
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DAIDO Yoshimasa
Computer and Network Systems Core, Kanazawa Institute of Technology
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KOBAYASHI Kaname
Computer and Network Systems Core, Kanazawa Institute of Technology
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HATTORI Shimmi
Computer and Network Systems Core, Kanazawa Institute of Technology
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Yasuura Hiroto
Faculty Of Engineering Kyushu University
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Tamaru Keikichi
Faculty Of Elctronics Kyoto University
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Tamaru Keikichi
Department Of Communications And Computer Engineering Kyoto University
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Hattori S
Kanazawa Inst. Of Technol. Ishikawa‐ken Jpn
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Yamaoka Masanao
Graduate School Of Informatics Kyoto University:(present Address) Hitachi Co. Ltd.
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Daido Y
Kanazawa Institute Of Technology
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Kobayashi Haruo
The Author Is With The Department Of Electronic Engineering Gunma University
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Kawabata Yutaka
Computer And Network Systems Core Kanazawa Institute Of Technology
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Minegishi Atsushi
Teratec Corporation Research And Development
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Nakamura Noritsugu
The Department Of Electronics And Communication Graduate School Of Engineering Kyoto University
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Kobayashi Y
Graduate School Of Informatics Kyoto University:(present Address) Hitachi Co. Ltd.
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Kobayashi Haruo
Dept. Of Veterinary Medicine Faculty Of Agriculture Iwate University
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Onodera Hidetoshi
The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive
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小野寺 秀俊
京都大学情報学研究科通信情報システム専攻:京都大学光・電子理工学教育研究センター
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Kobayashi Kazutoshi
Department of Applied Chemistry, Faculty of Science, Science University of Tokyo
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Kinoshita Masayoshi
Department of Applied Chemistry, Faculty of Engineering, Osaka City University
著作論文
- Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era(Electronic Circuits)
- Architecture and Performance Evaluation of a New Functional Memory : Functional Memory for Addition (Special Section on VLSI Design and CAD Algorithms)
- A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization (Special Section on VLSI for Digital Signal Processing)
- An LSI for Low Bit-Rate Image Compression Using Vector Quantization(Special Issue on Multimedia, Network, and DRAM LSIs)
- A Memory-Based Parallel Processor for Vector Quantization:FMPP-VQ (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture (Special Issue on New Architecture LSIs)
- A Quasi-Coherent Sampling Method for Wideband Data Acquisition(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
- A New Coherent Sampling System with a Triggered Time Interpolation(Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
- Capacity of Second-Order Bidirectional Associative Memory with Finite Neuron Numbers