Onodera Hidetoshi | Faculty of Engineering, Kyoto University

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概要

• Onodera Hidetoshiの詳細を見る
• 同名の論文著者
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関連著者

• Onodera Hidetoshi

  Faculty of Engineering, Kyoto University

• Tamaru Keikichi

  Faculty of Engineering, Kyoto University

• Onodera Hidetoshi

  Faculty Of Engineering Kyoto University

• Tamaru Keikichi

  Faculty Of Elctronics Kyoto University

• 小野寺 秀俊

  京都大学工学部電子工学科

• Onodera H

  Kyoto Univ. Kyoto‐shi Jpn

• Onodera Hidetoshi

  Kyoto Univ. Kyoto‐shi Jpn

• 小野寺 秀俊

  滋賀県立大学工学部

• 小野寺 秀俊

  京都大学大学院工学研究科電子通信工学専攻

• TAMARU Keikichi

  Okayama University of Science

• Tamaru K

  Okayama University Of Science

• Morie T

  Graduate School Of Life Science And Systems Engineering Kyushu Institute Of Technology

• Morie Takashi

  Faculty Of Engineering Kyoto University

• Kobayashi K

  Toyama Prefectural Univ. Toyama‐ken Jpn

• Okada Kazuhisa

  Faculty Of Engineering Kyoto University

• Yasuura Hiroto

  Faculty Of Engineering Kyoto University

• Hirata Akio

  Faculty Of Engineering Kyoto Sangyo University

• Hirata Akio

  Faculty Of Engineering Kyoto University

• Kobayashi Kensuke

  The Author Is With Lecroy Corp.

• KOBAYASHI Kazutoshi

  Faculty of Engineering, Kyushu University

• Kondo Masaki

  Faculty of Engineering, Kyoto University

• Kondo Masaki

  Department Of Electronics And Communication Kyoto University

• Kobayashi Kazutoshi

  Faculty Of Engineering Kyushu University

• Kobayashi K

  The Author Is With Lecroy Corp.

• Yasuura Hiroto

  Faculty Of Engineering Kyushu University

• Tamaru Keikichi

  Faculty Of Engineering Kyoto University

• Takeshita Kiyoshi

  Faculty of Engineering, Kyoto University

• Chen Guangqiu

  Faculty of Engineering, Kyoto University

• Takeshita Kiyoshi

  Faculty Of Engineering Kyoto University:yokogawa Hewlett Packard

• Chen Guangqiu

  Faculty Of Engineering Kyoto University

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著作論文

• Model-Adaptable Parameter Extraction System for MOSFET Models
• Development of Module Generators from Extracted Design Procedures : Application to Analog Device Generation
• A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture (Special Issue on New Architecture LSIs)
• Hardware Architecture for Kohonen Network (Special Issue on New Architecture LSIs)
• Compaction with Shape Optimization and Its Application to Layout Recycling
• Experiments with Power Optimization in Gate Sizing (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
• Estimation of Short-Circuit Power Dissipation for Static CMOS Gates (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)

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