Experiments with Power Optimization in Gate Sizing (Special Section of Letters Selected from the 1994 IEICE Spring Conference)

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概要

• 論文の詳細を見る

• In this paper, the power dissipation issue is considered in the gate sizing procedure. In order to observe the tradeoff among area, delay and power dissipation in a circuit, gate sizing algorithms which can minimize power under delay constraints or minimize area under power and delay constraints are formulated. Experiments are performed to investigate the properties of area-power-delay tradeoff in the gate sizing procedure.

• 社団法人電子情報通信学会の論文
• 1994-11-25

著者

• Onodera Hidetoshi

  Faculty of Engineering, Kyoto University

• Tamaru Keikichi

  Faculty of Engineering, Kyoto University

• Onodera Hidetoshi

  Faculty Of Engineering Kyoto University

• Tamaru Keikichi

  Faculty Of Engineering Kyoto University

• Tamaru Keikichi

  Faculty Of Elctronics Kyoto University

• Chen Guangqiu

  Faculty of Engineering, Kyoto University

• Chen Guangqiu

  Faculty Of Engineering Kyoto University

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