Compaction with Shape Optimization and Its Application to Layout Recycling

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概要

• 論文の詳細を見る

• We propose a new compaction problem that allows layout elements to have many shape possibilities. The objective of the problem is to find not only positions but also shapes of layout elements. We present an efficient method to solve the problem-compaction with shape optimization. This method simplifies the problem by considering the optimization of shapes only for the layout elements on a critical path. The layout is compacted step by step while Voptimizing the shapes of layout elements. Another importance of this compaction technique is that it makes layout to be "recyclable" for other set of device parameters. The experimental examples, which attempt shape optimization and recycle of analog layout, confirms the importance and efficiency of our method.

• 社団法人電子情報通信学会の論文
• 1995-02-25

著者

• Okada Kazuhisa

  Faculty Of Engineering Kyoto University

• Onodera Hidetoshi

  Faculty of Engineering, Kyoto University

• Tamaru Keikichi

  Faculty of Engineering, Kyoto University

• Onodera Hidetoshi

  Faculty Of Engineering Kyoto University

• Tamaru Keikichi

  Faculty Of Elctronics Kyoto University

関連論文

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• Development of Module Generators from Extracted Design Procedures : Application to Analog Device Generation
• A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture (Special Issue on New Architecture LSIs)
• A Language for Designing Module Generators (Special Issue on Synthesis and Verification of Hardware Design)
• Hardware Architecture for Kohonen Network (Special Issue on New Architecture LSIs)
• Compaction with Shape Optimization and Its Application to Layout Recycling
• Experiments with Power Optimization in Gate Sizing (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
• Estimation of Short-Circuit Power Dissipation for Static CMOS Gates (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
• The Trend of Functional Memory Development (Special Issue on LSI Memories)

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