Onodera Hidetoshi | Faculty Of Engineering Kyoto University
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概要
関連著者
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Onodera Hidetoshi
Faculty of Engineering, Kyoto University
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Tamaru Keikichi
Faculty of Engineering, Kyoto University
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Onodera Hidetoshi
Faculty Of Engineering Kyoto University
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Tamaru Keikichi
Faculty Of Elctronics Kyoto University
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小野寺 秀俊
京都大学工学部電子工学科
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Onodera H
Kyoto Univ. Kyoto‐shi Jpn
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Onodera Hidetoshi
Kyoto Univ. Kyoto‐shi Jpn
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小野寺 秀俊
滋賀県立大学工学部
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小野寺 秀俊
京都大学大学院工学研究科電子通信工学専攻
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TAMARU Keikichi
Okayama University of Science
著作論文
- Model-Adaptable Parameter Extraction System for MOSFET Models
- Development of Module Generators from Extracted Design Procedures : Application to Analog Device Generation
- A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture (Special Issue on New Architecture LSIs)
- Hardware Architecture for Kohonen Network (Special Issue on New Architecture LSIs)
- Compaction with Shape Optimization and Its Application to Layout Recycling
- Experiments with Power Optimization in Gate Sizing (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
- Estimation of Short-Circuit Power Dissipation for Static CMOS Gates (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)