小野寺秀俊 | 滋賀県立大学工学部

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概要

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著作論文

パネル討論 : 設計/CAD技術はディープサブミクロン時代の挑戦に耐えられるか
ばらつき考慮設計に向けて(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
ばらつき考慮設計に向けて(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
C-12-56 ω_nドメイン設計手法によるCDR-ICの低ジッタ化(C-12.集積回路,一般セッション)
Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling(Analog Circuits and Related SoC Integration Technologies)
Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line(Interconnect,VLSI Design and CAD Algorithms)
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Representative Frequency for Interconnect R(f)L(f)C Extraction(Parasitics and Noise)(VLSI Design and CAD Algorithms)
Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
PA-1 大学の研究をどのように産業界に活かすか?
相互結合インダクタを用いたTIA帯域向上手法(若手研究会)
AI-1-3 ディペンダブルVLSIプラットフォームへの挑戦(AI-1.デイベンダブルVLSIに向けて,依頼シンポジウム,ソサイエティ企画)
A 90nm 48×48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations(Low-Power and High-Performance VLSI Circuit Technology,VLSI Technology toward Frontiers of New Market)
A 90nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era(Electronic Circuits)
Experimental Study on Cell-Base High-Performance Datapath Design(IP Design)(VLSI Design and CAD Algorithms)
Experimental Study on Cell-Base High-Performance Datapath Design
Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,VLSI Design and CAD Algorithms)
Timing Analysis Considering Temporal Supply Voltage Fluctuation
Successive Pad Assignment for Minimizing Supply Voltage Drop(Power/Ground Network, VLSI Design and CAD Algorithms)
特集「システムLSI設計とその技術」の編集にあたって
アナログ/ディジタル混載LSIのCAD技術
Model-Adaptable Parameter Extraction System for MOSFET Models
Development of Module Generators from Extracted Design Procedures : Application to Analog Device Generation
Architecture and Performance Evaluation of a New Functional Memory : Functional Memory for Addition (Special Section on VLSI Design and CAD Algorithms)
A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization (Special Section on VLSI for Digital Signal Processing)
An LSI for Low Bit-Rate Image Compression Using Vector Quantization(Special Issue on Multimedia, Network, and DRAM LSIs)
A Memory-Based Parallel Processor for Vector Quantization:FMPP-VQ (Special Issue on New Concept Device and Novel Architecture LSIs)
A Current Mode Cyclic A/D Converter with Submicron Processes (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture (Special Issue on New Architecture LSIs)
Development of procedure for modeling MOSFET compatible with ITRS: noise and 1-5 characteristics modeling for RF/analog MOSFET (集積回路)
More Mooreに立ちはだかるCMOSばらつきの理解に向けて(低電力設計,システムオンシリコンを支える設計技術)
C-12-46 完全差動回路構成GVCOの高速化設計(C-12.集積回路,一般セッション)

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