Hashimoto Masanori | Osaka Univ. Suita‐shi Jpn

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概要

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著作論文

Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design(Interconnect,VLSI Design and CAD Algorithms)
Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,VLSI Design and CAD Algorithms)
Timing Analysis Considering Temporal Supply Voltage Fluctuation
Successive Pad Assignment for Minimizing Supply Voltage Drop(Power/Ground Network, VLSI Design and CAD Algorithms)
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance(Interconnect, VLSI Design and CAD Algorithms)
Transistor Sizing of LCD Driver Circuit for Technology Migration(Circuit Synthesis,VLSI Design and CAD Algorithms)
A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays(Circuit Synthesis,VLSI Design and CAD Algorithms)
Statistical Analysis of Clock Skew Variation in H-Tree Structure(Prediction and Analysis, VLSI Design and CAD Algorithms)
Impact of Self-Heating in Wire Interconnection on Timing
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
Proposal of Metrics for SSTA Accuracy Evaluation(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,VLSI Design and CAD Algorithms)
Gate Delay Estimation in STA under Dynamic Power Supply Noise
Impact of Well Edge Proximity Effect on Timing

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