Kurokawa Atsushi | Sanyo Electric Co. Ltd

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概要

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著作論文

Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model
An advanced effective capacitance model considering input waveform effect (第21回回路とシステム軽井沢ワークショップ論文集) -- (ばらつき関連技術)
Determination of Interconnect Structural Parameters for Best-and Worst-Case Delays(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Calculating the effective capacitance for interconnect loads based on thevenin model (VLSIのノイズ・タイミング解析)
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance(Interconnect, VLSI Design and CAD Algorithms)
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew(Prediction and Analysis, VLSI Design and CAD Algorithms)
A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads(Nonlinear Theory and its Applications)
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
Impact of Self-Heating in Wire Interconnection on Timing
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation(Interconnect,VLSI Design and CAD Algorithms)
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills(Interconnect, VLSI Design and CAD Algorithms)
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)
Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm(Power/Ground Network, VLSI Design and CAD Algorithms)
Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability
Simple Analytical Formulas for Estimating IR-Drops in an Early Design Stage
Prevention in a Chip of EMI Noise Caused by X'tal Oscillator
A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect

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