A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads(<Special Section>Nonlinear Theory and its Applications)
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概要
- 論文の詳細を見る
In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance C_<eff> concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate C_<eff>. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of C_<eff>. The introduction of Integration Approximation results in C_<eff> being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.
- 社団法人電子情報通信学会の論文
- 2005-10-01
著者
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INOUE Yasuaki
Graduate School of Information, Production and Systems, Waseda University
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HUANG Zhangcai
Graduate School of Information, Production and Systems, Waseda University
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Huang Zhangcai
Research Center Of Information Production And Systems Waseda University
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KUROKAWA Atsushi
Semiconductor Technology Academic Research Center (STARC)
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MAO Junfa
Shanghai Jiao Tong University
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Inoue Yasuaki
Graduate School Of Information Production And Systems Waseda University
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Huang Zhangcai
Graduate School Of Information Production And Systems Waseda University
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Inoue Yasuaki
Graduate School Of Ips Waseda University
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Kurokawa Atsushi
Sanyo Electric Co. Ltd.
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Kurokawa Atsushi
Sanyo Electric Co. Ltd
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