Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects

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概要

• 論文の詳細を見る

• A formula-based approach for extracting the inductance of on-chip VLSI interconnections is presented. All of the formulae have been previously proposed and are well-known, but the degrees of accuracy they provide in this context have not previously been examined. The accuracy of the equations for a 0.1μm technology node is evaluated through comparison of their results with those of 3-D field solvers. Comprehensive evaluation has proven that the maximum relative error of self- and mutual inductances as calculated by the formulae are less than 5% for parallel wires and less than 13% for angled wires, when wire width is limited to no more than 10 times the minimum. When applied to a realistic example with 43 wire segments, a program using the formula-based approach extracts values more than 60 times faster than a 3-D field solver.

• 社団法人電子情報通信学会の論文
• 2003-04-01

著者

• SATO Takashi

  Kyoto University

• Sakata Tsuyoshi

  Fujitsu Microelectronics Ltd.

• KUROKAWA Atsushi

  Semiconductor Technology Academic Research Center (STARC)

• Sato T

  Photonic Lattice Inc.:niche Tohoku University

• Masuda Hiroo

  Semiconductor Technology Academic Research Center (starc)

• Masuda Hiroo

  Renesas Technology Corp.

• Masuda Hiroo

  Semiconductor Technology Academic Research Center

• HACHIYA Kotaro

  NEC Corp.

• SATO Takashi

  Hitachi,Ltd.

• TOKUMASU Kazuya

  Semiconductor Technology Academic Research Center(STARC)

• Hachiya Kotaro

  Jedat Inc.

• Sato Takashi

  Institute Of Physics And Tsukuba Research Center For Interdisciplinary Materials Science University

• Sato Takashi

  Hitachi Ltd.

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