A Method to Derive SSO Design Rule Considering Jitter Constraint(<Special Section>Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
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概要
- 論文の詳細を見る
A method to derive design rules for SSO (Simultaneous Switching Outputs) considering jitter constraint on LSI outputs is proposed. Since conventional design rules do not consider delay change caused by SSO, timing errors have sometimes occurred in output signals especially for a high-speed memory interface which allows very small jitter. A design rule derived by the proposed method includes delay change characteristics of output buffers to consider the jitter constraint. The rule also gives mapping from the jitter constraint to constraint on design parameters such as effective power/ground inductance, number of SSO and drivability of buffers.
- 社団法人電子情報通信学会の論文
- 2006-04-01
著者
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Oka Hiroki
Ntt Advanced Technology Corporation:(present Office)nippon Telegraph And Telephone Corporation
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SATO Takashi
Kyoto University
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Sakata Tsuyoshi
Fujitsu Microelectronics Ltd.
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Sato T
Photonic Lattice Inc.:niche Tohoku University
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KOBAYASHI Hiroyuki
Nihon Synopsys Co., Ltd.
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OKUMURA Takaaki
Fujitsu VLSI Ltd.
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HACHIYA Koutaro
NEC Electronics Corp.
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SATO Takashi
Renesas Technology Corporation
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Hachiya Kotaro
Jedat Inc.
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Kobayashi Hiroyuki
Nihon Synopsys Co. Ltd.
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Sato Takashi
Institute Of Physics And Tsukuba Research Center For Interdisciplinary Materials Science University
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Okumura Takaaki
Semiconductor Technol. Academic Res. Center
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