On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design(Prediction and Analysis, <Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper quantitatively analyzes thermal gradient of SoC and proposes a thermal flattening procedure. First, the impact of dominant parameters, such as area occupancy of memory/logic block, power density, and floorplan on thermal gradient are studied quantitatively. Temperature difference is also evaluated from timing and reliability standpoints. Important results obtained here are 1) the maximum temperature difference increases with higher memory area occupancy and 2) the difference is very floorplan sensitive. Then, we propose a procedure to amend thermal gradient. A slight floorplan modification using the proposed procedure improves on-chip thermal gradient significantly.

• 社団法人電子情報通信学会の論文
• 2005-12-01

著者

• SATO Takashi

  Kyoto University

• HASHIMOTO Masanori

  Graduate School of Information Science and Technology, Osaka University

• Sakata Tsuyoshi

  Fujitsu Microelectronics Ltd.

• Sato T

  Photonic Lattice Inc.:niche Tohoku University

• Masuda Hiroo

  Renesas Technology Corp.

• ONO Nobuto

  Jedat Inc.

• ICHIMIYA Junji

  Ricoh Corporation

• HACHIYA Koutaro

  NEC Electronics Corp.

• SATO Takashi

  Renesas Technology Corporation

• Hachiya Kotaro

  Jedat Inc.

• Ichimiya Junji

  Ricoh Corporation:(present Office)fujitsu Limited

• Sato Takashi

  Institute Of Physics And Tsukuba Research Center For Interdisciplinary Materials Science University

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