Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis
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概要
- 論文の詳細を見る
Random variations in Id-Vg characteristics of MOS transistors in an LSI chip are shown to be concisely characterized by using only 3 transistor parameters (Vth, β0, υSAT) in the MOS level 3 SPICE model. Statistical analyses of the transistor parameters show that not only the threshold voltage variation, ΔVth, but also the current factor variation, Δβ0, independently induces Id-variation, and that Δβ0 is negatively correlated with the saturation velocity variation, ΔυSAT. Using these results, we have proposed a simple method that effectively takes the correlation between parameters into consideration when creating statistical model parameters for designing a circuit. Furthermore, we have proposed a sensitivity analysis methodology for estimating the process window of SRAM cell operation taking transistor variability into account. By applying the concise statistical model parameters to the sensitivity analysis, we are able to obtain valid process windows without the large volume of data-processing and long turnaround time associated with the Monte Carlo simulation. The processs window was limited not only by ΔVth, but also by Δβ0 which enhanced the failure region in the process window by 20%.
- （社）電子情報通信学会の論文
- 2008-04-01
著者
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AOKI Masakazu
Electronic Systems Engineering, Tokyo University of Science
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Masuda Hiroo
Renesas Technol. Corp. Kodaira‐shi Jpn
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Masuda Hiroo
Renesas Technology Corp.
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Aoki Masakazu
Electronic Systems Engineering Tokyo University Of Science
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OHKAWA Shin-ichi
Renesas Technology Corp.
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Masuda Hiroo
Renesas Electronics Corporation, Takasaki, Gunma 370-0021, Japan
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