On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature(Simulation and Verification,<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• In this paper, we propose a methodology for calculating on-chip temperature gradient and leakage power distributions. It considers the interdependence between leakage power and local temperature using a general circuit simulator as a differential equation solver. The proposed methodology can be utilized in the early stages of the design cycle as well as in the final verification phase. Simulation results proved that consideration of the temperature dependence of the leakage power is critically important for achieving reliable physical designs since the conventional temperature analysis that ignores the interdependence underestimates leakage power considerably and may overlook potential thermal runaway.

• 社団法人電子情報通信学会の論文
• 2006-12-01

著者

• SATO Takashi

  Kyoto University

• HASHIMOTO Masanori

  Graduate School of Information Science and Technology, Osaka University

• SATO Takashi

  Integrated Research Institute, Tokyo Institute of Technology

• Sakata Tsuyoshi

  Fujitsu Microelectronics Ltd.

• Sato T

  Photonic Lattice Inc.:niche Tohoku University

• Masuda Hiroo

  Renesas Technology Corp.

• ONO Nobuto

  Jedat Inc.

• ICHIMIYA Junji

  Ricoh Corporation

• Ichimiya Junji

  Ricoh Corporation:(present Office)fujitsu Limited

• Sato Takashi

  Institute Of Physics And Tsukuba Research Center For Interdisciplinary Materials Science University

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