Physical design challenges to nano-CMOS circuits
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概要
- 論文の詳細を見る
There are many challenges inherent in the design of nano-CMOS. This paper describes our recent work relating to the physical design of CMOS circuits. First, in line with variation-aware design, a novel ingenious method of measuring variations in subthreshold characteristics is described. Next, recent RF CMOS issues and approaches to nano-CMOS are discussed. Finally, an on-chip transmission line interconnect developed for global wiring is discussed.
- The Institute of Electronics, Information and Communication Engineersの論文
著者
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Masu Kazuya
Integrated Research Institute
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Amakawa Shuhei
Integrated Research Institute Tokyo Institute Of Technology
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SATO Takashi
Integrated Research Institute, Tokyo Institute of Technology
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Ishihara Noboru
Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
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MASU Kazuya
Integrated Research Institute, Tokyo Institute of Technology
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Nakayama Noriaki
Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology
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Ishihara Noboru
Integrated Research Institute, Tokyo Institute of Technology
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