Optimization Methodology of Layer Numbers with Circuit/Process Co-Design
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概要
- 論文の詳細を見る
The number of layers directly affects manufacturing cost, and it also has a trade-off with the circuit area in multilevel interconnection LSI. In this paper, we propose a co-design methodology for circuits and processes to optimize the number of interconnect layers. In the proposed methodology, the number of interconnect layers can be optimized in consideration of circuit area. Wire length distribution (WLD) is used to derive the optimized number of layers from a circuit netlist. Operating frequency and power consumption are estimated as functions of circuit area in the 180 nm process-technology node. From the analyzed results, it has been shown that circuit area has an optimum value to improve both operating frequency and power consumption.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2006-04-15
著者
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Masu Kazuya
Integrated Research Institute
-
Okada Kenichi
Integrated Research Institute Tokyo Institute Of Technology
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Uezono Takumi
Integrated Research Institute Tokyo Institute Of Technology
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INOUE Junpei
Integrated Research Institute Laboratory, Tokyo Institute of Technology
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NAKASHIMA Hidenari
Integrated Research Institute Laboratory, Tokyo Institute of Technology
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Kyogoku Takanori
Integrated Research Institute Laboratory Tokyo Institute Of Technology
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Kyogoku Takanori
Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
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Inoue Junpei
Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
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Uezono Takumi
Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
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Nakashima Hidenari
Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
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