Statistical Modeling of a Via Distribution for Yield Estimation(Interconnect,<Special Section>VLSI Design and CAD Algorithms)
スポンサーリンク
概要
- 論文の詳細を見る
In this paper, we propose a via distribution model for yield estimation. This model expresses a relationship between the number of vias and wire length. We also provide an estimate for the total number of vias in a circuit, derived from the via distribution and the wire-length distribution. The via distribution is modeled as a function of track utilization, and the wire-length distribution can be derived from the gate-level netlist and the layout area. We extract model parameters from the commercial chips designed for 0.18-μm and 0.13-μm CMOS processes, and demonstrate the yield degradation caused by vias.
- 社団法人電子情報通信学会の論文
- 2006-12-01
著者
-
Masu Kazuya
Integrated Research Institute
-
Okada Kenichi
Integrated Research Institute Tokyo Institute Of Technology
-
UEZONO Takumi
Integrated Research Institute, Tokyo Institute of Technology
-
Uezono Takumi
Integrated Research Institute Tokyo Institute Of Technology
-
Masu Kazuya
Solutions Research Laboratory Tokyo Institute Of Technology
-
Okada Kenichi
Tokyo Inst. Of Technol. Yokohama‐shi Jpn
関連論文
- Wide-band, high linear low noise amplifier design in 0.18um CMOS technology
- Lower Boundary of Supply Voltage in Digital ULSI Based on the Communication Theory
- Low Power Current-Cut Switched-Current Matched Filter for CDMA (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
- Novel Low-Power Switched-Current Matched Filter for Direct-Sequence Code-Division-Multiple-Access Wireless Communication
- Full-Duplex Asynchronous Spread Spectrum Modem Using a SAW Convolver for 2.4-GHz Wireless LAN (Special Issue on Personal, Indoor and Mobile Radio Communications)
- A Universal Equivalent Circuit Model for Ceramic Capacitors
- Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress
- C-12-43 CMOS Power Amplifier in 65nm Technology
- C-12-37 CMOS Inverter-based Wideband LNA in 65nm Technology
- An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis
- Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits
- 2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept
- A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation
- One-Shot Voltage-Measurement Circuit Utilizing Process Variation
- Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network
- Reconfigurable RF CMOS Circuit for Cognitive Radio
- A High-Efficiency CMOS Class-B Push-Pull Power Amplifier for Code-Division-Multiple-Access Cellular System
- Aluminum Chemical Vapor Deposition Technology for High Deposition Rate and Surface Morphology Improvement
- Crystallographic Structures and Parasitic Resistances of Self-Aligned Silicide TiSi_2/Self-Aligned Nitrided Barrier Layer/Selective Chemical Vapor Deposited Aluminum in Fully Self-Aligned Metallization Metal Oxide Semiconductor Field-Effect Transistor
- Self-Aligned 10-nm Barrier Layer Formation Technology for Fully Self-Aligned Metallization Metal-Oxide-Semiconductor Field-Effect-Transistor
- Self-Aligned 10-nm Barrier Layer Formation Technology for Fully Self-Aligned Metallization MOSFET
- Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit
- A 0.49-6.50GHz Wideband LC-VCO with High-IRR in a 180nm CMOS Technology
- Novel Low-Power Switched Current Matched Filter for DS-CDMA Wireless Communication
- In-Situ Counting of Process-Induced Particles
- Particle Counting in Semiconductor Processing Gas and Apparatus with a New Flow-Cell-Type Laser Particle Counter
- Single Crystallization of Aluminum on SiO_2 by Thermnal Annealing and Observation with Scanning μ-RHEED Microscope
- Development of Scanning μ-RHEED Microscopy for Imaging Polycrystal Grain Structure in LSI (SOLID STATE DEVICES AND MATERIALS 1)
- High-Rate Deposition of High-Quality Silicon Nitride Film at Room Temperature by Quasi-Remote Plasma Chemical Vapor Deposition
- A Large Variable Ratio On-Chip Inductor with Spider Legs Shield
- Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit(Analog Circuit Techniques and Related Topics)
- Small Area Snake Inductor on Si RF CMOS Chip
- On-chip Spiral Inductors Integrated with Wafer-Level Package
- In Situ Observation of Electromigration in Cu Film Using Scanning μ-Reflection High-Energy Electron Diffraction Microscope
- Planarized Deposition of High-Quality Silicon Dioxide Film by Photoassisted Plasma CVD at 300℃ Using Tetraethyl Orthosilicate
- Evaluation of LaB_6 Thin Film as Low-Work-Function Gate for MOSFET Operated at Low Temperature
- Silicon Nitride Films with Low Hydrogen Content, Low Stress, Low Damage and Stoichiometric Composition by Photo-Assisted Plasma CVD
- Temperature-Scaling Theory for Low-Temperature-Operated MOSFET with Deep-Submicron Channel : Semiconductors and Semiconductor Devices
- Pyrolysis and Photolysis of Trimethylaluminum
- C-12-23 A Study of Inverter-based RF CMOS Low Noise Amplifier Scalability in CMOS Process
- C-2-82 Broadside 3-dB Tandem Coupler Using WLP Technology for 60 GHz Applications
- Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology(Microwaves, Millimeter-Waves)
- On-Chip Yagi Antenna for Wireless Signal Transmission in Stacked MCP
- Zero-Crosstalk Bus Line Structure for Global Interconnects in Si Ultra Large Scale Integration
- RF Passive Components Using Metal Line on Si CMOS(Analog Circuit and Device Technologies)
- Zero-Crosstalk Bus Line Structure for Global Interconnects in Si ULSI
- High-Speed Transmission Circuit for Micro Network on Si ULSI
- Twisted Differential Transmission Line Structure for EMI Noise Reduction at Global Interconnect in Si LSI
- High Density Differential Transmission Line Structure on Si ULSI(Analog Circuit and Device Technologies)
- Statistical Modeling of a Via Distribution for Yield Estimation(Interconnect,VLSI Design and CAD Algorithms)
- Wire Length Distribution Model for System LSI(Interconnect, VLSI Design and CAD Algorithms)
- Evaluation of X Architecture Using Interconnect Length Distribution(Interconnect, VLSI Design and CAD Algorithms)
- Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model(Prediction and Analysis, VLSI Design and CAD Algorithms)
- RF Attenuation Characteristics for In Vivo Wireless Healthcare Chip
- Optimization Technique of Number of Interconnect Layers and Circuit Area Based on Wire Length Distribution
- in-vivo Wireless Communication System for Bio MEMS Sensors
- 2.4--10 GHz Low-Noise Injection-Locked Ring Voltage Controlled Oscillator in 90 nm Complementary Metal Oxide Semiconductor
- Equivalent Circuit Model for On-Chip Variable Inductor
- Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence
- A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio
- RF CMOS Integrated Circuit : History, Current Status and Future Prospects
- Matched Filter Type SET Circuit for Room Temperature Operation
- Reliability of Single Electron Transistor Circuits Based on E_b/N_0-Bit Error Rate Characteristics
- Low-Temperature Metal-Oxide-Semiconductor Field-Effect Transistor Operation by Temperature Scaling Theory
- Eigenmode Analysis of Propagation Constant for a Microstrip Line with Dummy Fills on a Si CMOS Substrate
- An Inductorless Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS (集積回路)
- 0.1V 13GHz Transformer-Based Quadrature Voltage-Controlled Oscillator with a Capacitor Coupling Technique in 90nm Complementary Metal Oxide Semiconductor (Special Issue : Solid State Devices and Materials (2))
- RF signal generator using time domain harmonic suppression technique in 90nm CMOS
- A Three-Stage Inverter-Based Stacked Power Amplifier in 65 nm Complementary Metal Oxide Semiconductor Process
- A Study of Digitally Controllable Radio Frequency Micro Electro Mechanical Systems Inductor
- Planar Solenoidal Inductor in Radio Frequency Micro-Electro-Mechanical Systems Technology for Variable Inductor with Wide Tunable Range and High Quality Factor
- 1.2--17.6 GHz Ring-Oscillator-Based Phase-Locked Loop with Injection Locking in 65 nm Complementary Metal Oxide Semiconductor
- An Inverter-Based Wideband Low-Noise Amplifier in 40 nm Complementary Metal Oxide Semiconductor
- Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique
- On-Chip Yagi–Uda Antenna for Horizontal Wireless Signal Transmission in Stacked Multi Chip Packaging
- A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65nm CMOS
- An Inductorless Phase-Locked Loop with Pulse Injection Locking Technique in 90nm CMOS
- Optimization Methodology of Layer Numbers with Circuit/Process Co-Design
- Fractionally Injection-Locked Frequency Multiplication Technique with Multi-Phase Ring Voltage-Controlled Oscillator
- C-12-11 Indutors and Transformers on 65 nm CMOS Technology for 60 GHz Applications
- Fractionally Injection-Locked Frequency Multiplication Technique with Multi-Phase Ring Voltage-Controlled Oscillator (Special Issue : Solid State Devices and Materials)
- Physical design challenges to nano-CMOS circuits
- C-12-21 Crossing Transmission Line Modeling Using Two-port Measurements
- C-12-23 A1.8 GHz, 2.2 Watt Fully Integrated CMOS Power Amplifier
- A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65nm CMOS