A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65nm CMOS

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概要

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• This paper proposes a low-phase-noise ring-VCO-based frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34GHz with reference signals of 528MHz was -119dBc/Hz.

著者

• MASU Kazuya

  Solutions Research Laboratory, Tokyo Institute of Technology

• Tanoi Satoru

  Solution Science Research Laboratory (SSRL), Tokyo Institute of Technology

• Masu Kazuya

  Solutions Research Laboratory Tokyo Institute Of Technology

• Ishihara Noboru

  Solutions Research Laboratory Tokyo Institute Of Technology

• Ito Hiroyuki

  Solutions Research Laboratory, Tokyo Institute of Technology

• Lee Sang_yeop

  Solutions Research Laboratory Tokyo Institute Of Technology

• Kamimura Tatsuya

  Solutions Research Laboratory, Tokyo Institute of Technology, Yokohama 226-8503, Japan

• Ikeda Sho

  Solutions Research Laboratory, Tokyo Institute of Technology, Yokohama 226-8503, Japan

• KANEMARU Norifumi

  Solutions Research Laboratory, Tokyo Institute of Technology

• IKEDA Sho

  Solutions Research Laboratory, Tokyo Institute of Technology

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