Optimization Technique of Number of Interconnect Layers and Circuit Area Based on Wire Length Distribution
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概要
- 論文の詳細を見る
- 2004-09-15
著者
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Masu Kazuya
Precision And Intelligence Laboratory Tokyo Institute Of Technology
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Okada Kenichi
Integrated Research Institute Tokyo Institute Of Technology
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OKADA Kenichi
Precision and Intelligence Laboratory, Tokyo Institute of Technology
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NAKASHIMA Hidenari
NEC Electronics Corp.
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KYOGOKU Takanori
Precision and Intelligence Laboratory, Tokyo Institute of Technology
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INOUE Junpei
Precision and Intelligence Laboratory, Tokyo Institute of Technology
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NAKASHIMA Hidenari
Precision and Intelligence Laboratory, Tokyo Institute of Technology
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Inoue Junpei
Integrated Research Institute Tokyo Institute Of Technology
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Kyogoku Takanori
Integrated Research Institute Laboratory Tokyo Institute Of Technology
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Nakashima Hidenari
Integrated Research Institute Tokyo Institute Of Technology
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Masu Kazuya
Solutions Research Laboratory Tokyo Institute Of Technology
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Okada Kenichi
Tokyo Inst. Of Technol. Yokohama‐shi Jpn
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